Method and system for improving reliability of memory device

Abstract

A system for improving reliability of a memory device includes one or more memory banks, each of which has one or more regular memory cell rows and one or more redundant memory cell rows. At least one built-in-self-test (BIST) unit is coupled to the memory banks for testing the redundant memory cell rows to determine their respective quality standards, and testing the regular memory cell rows to identify the regular memory cell row that fails to pass a predetermined quality standard. At least one built-in-self-repair (BISR) unit is coupled to the BIST unit for replacing the failed regular memory cell row with the redundant memory cell row having a quality standard equal to or higher than the predetermined quality standard. The BIST unit repeatedly tests the regular memory cell rows a number of times, with each time applying a different quality standard.

Description

technical field

[0001] The present invention relates to an integrated circuit (IC) design, and more particularly to a system and method for improving the reliability of a memory device. Background technique

[0002] A memory device generally includes a plurality of memory banks, and the memory banks are respectively coupled to a plurality of circuit modules that control their operations. A memory block usually includes a plurality of memory cells arranged in rows and columns. In addition to these regular memory cell rows, the memory block also includes a redundant memory cell row. Traditionally, this spare column of memory cells is reserved to replace a defective primary column of memory cells. By re-addressing the spare memory cell row to the failed main memory cell row, the above replacement can be accomplished without re-changing the actual wiring layout of the memory device.

[0003] Generally speaking, the spare memory cell rank is only used when the main memory cell...

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