Self error-correcting high speed scalar frequency divider with large range in integrate circuit chip

Abstract

A self error-correcting high speed scalar frequency divider with large range in an integrate circuit chip relates to the frequency divider technology in a digital circuit, and includes a multistage latch, wherein the former two stages are basic modules, and the other are expanding module, each latch is composed of a high turning on latch and a low turning on latch, in which one latch is set as an input latch, and the other latch is set as an output latch; the connection of each adjacent latch in the frequency divider is the connection of different clock turning on latch; in the latch connection of the expanding module, a logical expression is arranged, wherein N>n>=2, BIN is an input end of a transmission gate of the Nth stage input latch, OIN-1 is an output end of the N-1th stage input latch, S is a selective signal input end of the Nth stage input latch, OON is an output end of the Nth stage output latch, OON-n is an output end of the N-nth stage output latch. Such a structure can realize the whole self error-correcting function of the frequency divider.

Description

technical field [0001] The invention relates to frequency divider technology in digital circuits, in particular to a high-speed and large-range frequency divider technology for microprocessor clock circuits in the technical field of integrated circuit chips. Background technique [0002] Clock circuits in modern high-speed microprocessors are usually generated by multiplying the input clock frequency with one or more phase-locked loops. An important component of this method of frequency doubling is the frequency divider in the phase-locked loop feedback loop. This crossover needs to be able to handle high frequency signals. Different product performance and the frequency conversion function of the microprocessor generally require that the value of the frequency division ratio can be adjusted. There are many types of high-speed frequency dividers to achieve different functional requirements and performance indicators. One type of frequency divider requires that the output ...

AI Technical Summary

Problems solved by technology

[0009] The illegal cycle is actually a 1 / 2 frequency division. After the number of counters increases, the complexity of the illegal cycle increases, forming multiple different illegal cycles. After entering the illegal cycle, the frequency division results are very confusing.

[0010] Another similar frequency divider is a high-speed counter using LFSR (Linear Feedback Shift Register) encoding. Such as image 3 As shown, the frequency divider composed of N-level registers has a frequency division range of 2-2 N The index rises, and thus belongs to the binary counter. The advantage of this frequency divider is that the structure of the main frequency divider is simple, such as Figure 4 As shown, after adding a 2-frequency divider feedback circuit, a nearly symmetrical output clock can be generated. However, the speed of the frequency divider decreases after the number of stages of the frequency divider increases. Programmable function, after the number of stages increases, the logic design of the random code decoder will become very complicated.

[0011] So the current problems of this kind of frequency divider: a. The speed bottle diameter problem of the large-scale programmable frequency divider; b. The lower limit of the frequency division range of the traditional Johnson counter is limited by the programming function and the self-error correction function; c. The illegal cycle self-correction function of the Johnson counter needs to be completed in one clock cycle

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