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Semiconductor device and wire bonding method used for the same

A semiconductor and wire connection technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., which can solve problems such as increasing bond pads and contact dimensions

Inactive Publication Date: 2008-02-20
YAMAHA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This also increases the size of the bond pad and contact

Method used

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  • Semiconductor device and wire bonding method used for the same
  • Semiconductor device and wire bonding method used for the same
  • Semiconductor device and wire bonding method used for the same

Examples

Experimental program
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Effect test

no. 1 approach

[0068] A semiconductor device 1 according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 4 . As shown in FIGS. 1 and 2, a plurality of pins 7 and 9 arranged adjacent to each other are arranged on the periphery of a semiconductor chip 5 mounted on a stage 3 having a planar shape, wherein the pin 7 is electrically connected via three leads 15 to 17. to three electrode pads 19 to 21, and the pin 9 is electrically connected to three electrode pads 23 to 25 via three lead wires 15 to 17. A plurality of sets of pins connected via three leads and three electrodes are arranged for the semiconductor chip 5 .

[0069] Each pin 7 and 9 has an elongated shape extending toward the semiconductor chip 5 . The second bonding objects L11 to L13 connected to the leads 11 to 13 are arranged longitudinally along the lead wire 7 , and the second bonding objects L21 to L23 connected to the leads 15 to 17 are arranged longitudinally along the lead wire...

no. 2 approach

[0102] Next, a wire bonding method according to a second embodiment of the present invention will be described with reference to FIGS. 7A to 7C , FIGS. 8A and 8B , FIGS. 9A to 9C , FIGS. 10A and 10B , and FIGS. 11A and 11B . As shown in FIGS. 7A-7C, 8A, 8B, 9A, and 9B, a wire bonding method is performed so that bonding pads 101a formed on a semiconductor chip 101 mounted on a board 103 and bonding pads 101a formed on the board 103 are connected via metal wires 105. Electrical connections are established between electrode pads (or connection pads) 103a around the semiconductor chip 101 .

[0103] As shown in FIG. 7A , the semiconductor chip 101 is pre-mounted on the board 103 such that electrode pads 103 a are formed on the board 103 at the periphery of the semiconductor chip 101 . Here, the small-diameter capillary 109 is used to provide the thin lead wire 107 whose diameter is smaller than that of the metal wire 105 . The tip of the small-diameter capillary 109 is pressed on...

no. 3 approach

[0131] A semiconductor device 201 according to a third embodiment of the present invention will be described with reference to FIGS. 12 to 14 . As shown in FIGS. 12 and 13 , a semiconductor chip 205 is mounted on a surface 203a of a stage 203 having a planar shape in plan view, with a plurality of electrode pads 207 and 209 formed on the surface 205a of the semiconductor chip 205 . A plurality of pins 211 and 213 line the periphery of the semiconductor chip 205 in which they are connected to electrode pads 207 to 209 via a plurality of leads 215 to 217 .

[0132]In the semiconductor chip 201, the stage 203, the semiconductor chip 205, and the leads 215 and 217 are sealed with the mold resin 219, and the mold resin 219 also integrally fixes the stage 203, the semiconductor chip 205, the pins 211 and 213, and the leads 215 and 217. at the intended location.

[0133] The electrode pads 207 and 209 are alternately arranged along different lines on the surface 205 a of the semicon...

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PUM

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Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of electric short circuits between the most closely arranged wires out of a plurality of wires for connecting individual groups of electrode pads of a semiconductor chip and two leads arranged adjacent to each other around the semiconductor chip, respectively.SOLUTION: In the semiconductor device 1, second bonds of each three wires 11-13 and 15-17 of each lead 7 and 9 are arranged in the longitudinal direction of the leads 7 and 9. The three first wires 11-13 connected to one lead 7 are connected to the electrode pads 19-21 in a first row arranged in the arranging direction of the leads 7 and 9, while the three second wires 15-17 connected to the other lead 9 are connected to the electrode pads 23-25 in a second row arranged further away from the leads 7 and 9 than those in the first row. The first wire 13 connected to the most posteriorly located second bond of the lead 7 is connected to other electrode pad 20 in the first row than the electrode pad 21 in the first row which is closest to the electrode pads 23-25 in the second row.

Description

technical field [0001] The present invention relates to a semiconductor device and a wire bonding method therefor. The present invention also relates to a method of manufacturing a semiconductor device using a lead frame. Background technique [0002] Japanese Unexamined Patent Application Publication No. H06-302638 teaches an example of a semiconductor device in which bonding wires are arranged so as not to contact each other, in which electrode pads of a semiconductor chip are respectively electrically connected via wires to pins arranged at the periphery of the semiconductor chip . In this semiconductor device, when the current flowing between the electrode pad and the lead increases, the lead is heated and melted, or voids are undesirably caused due to alloy diffusion of the bonding portion between the lead and the lead. [0003] A conventionally known method of solving the above disadvantages is achieved by a structure in which a plurality of leads are arranged betwee...

Claims

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Application Information

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IPC IPC(8): H01L23/488H01L21/60H01L23/485H01L23/495
CPCH01L2924/01082H01L2924/00014H01L24/06H01L2924/10157H01L2924/01004H01L2224/48465H01L24/05H01L2224/451H01L2224/48095H01L2224/49113H01L2924/01002H01L2224/48247H01L2224/04042H01L2924/01005H01L2924/01033H01L2924/01006H01L2924/01029H01L2224/05556H01L2224/49171H01L24/48H01L2224/05554H01L24/49H01L2224/48H01L2224/49H01L2224/78301H01L2924/181
Inventor 大川真也
Owner YAMAHA CORP
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