Asynchronous clock data transmission device and method

Abstract

The device includes following units: counting unit for global clock (CUGC) in use for indicating serial number of the input data in fast source clock domain; being connected to CUGC, multichannel allocation and control unit (MACU) in use for sampling the input data circularly based on serial number of data; being connected to MACU, the synchronous control unit (SCU) in use for synchronizing the sampled data with target clock domain; being connected to SCU, the word assembling unit in use for assembling the synchronized data by SCU into the assembled data. The method includes steps: indicating serial number of the input data in fast source clock domain; based on serial number of the data to sample the input data circularly through multiple data channels; synchronizing the sampled data with target clock domain; assembling the synchronized data into the assembled data and outputting the data. Features are: raising transmission efficiency, and simple control method.

Description

Technical field [0001] The invention relates to an asynchronous clock data transmission device and method, in particular to an asynchronous clock data transmission device and method when data is transmitted from a fast source clock domain to a slow target clock domain. Background technique [0002] In engineering design, most applications related to data transmission involve data movement across clock domains, such as commonly used disk controllers and network processors. When a signal is transferred from one clock domain to another, it needs to be treated as an asynchronous signal. For asynchronous signal processing, the most basic problem is to solve the problem of signal stability. If it is not solved well, the received asynchronous signal may be in an unstable state, such as in a metastable state, and may cause the unstable state to be in a new state. Spread within the clock domain, causing system malfunctions. Therefore, when a signal traverses between asynchronous clock dom...

AI Technical Summary

Problems solved by technology

Although there are relatively mature technologies to solve these problems, when transferring data from the fast clock domain to the slow clock domain, the speed of data writing is faster than the speed of data output on the side of the slow clock domain. When using the FIFO structure, the storage space of the FIFO must be set to be infinite, otherwise it will cause data accumulation effect and data overflow problem

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