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Data processing system and method for memory defragmentation

A data processing system and memory technology, applied in memory systems, electrical digital data processing, instruments, etc., can solve the problem of memory becoming fragmented

Inactive Publication Date: 2008-04-16
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, if this second task stops, the memory becomes fragmented since the address range between the two tasks is not occupied by any task's data
Therefore, it may happen that another task requests write access to the FIFO memory, but is denied, even though there is enough space in the FIFO memory, because the space is not associated by a common address range, but on the FIFO memory. pieces of

Method used

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  • Data processing system and method for memory defragmentation
  • Data processing system and method for memory defragmentation

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Embodiment Construction

[0021] The architecture of the preferred embodiment of the present invention is specifically designed to handle continuous media streams in a multi-processing environment, ie, the architecture is designed for media processing applications and can be reconfigured at runtime without significant performance degradation. Signal processing for such media applications includes stream-based processing utilizing FIFO periodic communication behavior. Effective logical FIFO implementations require that the address range of a FIFO be contiguous such that the next word in the FIFO can be found by incrementing the pointer in the FIFO.

[0022] figure 1 A block diagram showing the construction of a system on chip according to a preferred embodiment of the present invention. The system comprises a first and a second processing unit PU1, PU2, a memory means MEM and an address translation unit ATU. The first and second processing units PU1, PU2 are each connected to a memory and to an addres...

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Abstract

A data processing system is provided in a stream-based communication environment. The data processing system comprises at least one processing unit (PUl, PU2) for a stream-based processing of a plurality of processing jobs (J1-J5), a memory means (MEM) having an address range; and a plurality of FIFOs memory mapped to part of the address range of the memory means (MEM), respectively. Each of the FIFOs is associated to one of said plurality of processing jobs (jl-j5) to enable their communication. An address translation unit (ATU) is provided for identifying address ranges in the memory means (MEM) which are not currently used by the plurality of FIFOs and for moving the address range of at least one FIFO to a currently unused address range in the memory means (MEM).

Description

technical field [0001] The invention relates to a data processing system comprising at least one processing unit and a memory, and a method for memory defragmentation within the data processing system. Background technique [0002] In modern embedded systems, especially those used for stream processing, the management of available (on-chip) memory is very important for their overall performance. Typically, a memory manager is provided to manage memory. Management is basically performed through the process of allocating and freeing parts of memory. Memory can be divided into blocks. Allocation is performed by requesting an address space of n consecutive bytes, and returning a pointer indicating such address space. Release is performed by freeing the indicated address space or block when it is no longer needed. Additionally, the memory manager keeps track of unallocated or free blocks between allocated blocks. However, with successive allocations and deallocations, memory...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/02
CPCG06F12/023
Inventor 马克·J·G·贝库依
Owner NXP BV
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