Stacking chip encapsulation structure with multi-section bus bar in lead rack

Abstract

The invention provides a stacked chip encapsulation structure with a multi-stage collecting bar in a lead frame, which includes a lead frame consisting of a plurality of inner pin groups arranged relatively, a plurality of outer pin groups and a chip bearing seat, wherein, the chip bearing seat is arranged among a plurality of inner pin groups arranged relatively and forms height difference with the inner pin groups; the stacked chip device is formed by a plurality of chip stacks and arranged on the chip bearing seat and is electrically connected with the inner pin groups; and an encapsulationbody, used to wrap the stacked chip device and the lead frame, wherein, the lead frame includes at least one collecting bar in multi-stage type and is arranged among the inner pin groups and the chipbearing seat.

Description

technical field [0001] The invention relates to a multi-chip offset stacking packaging structure, in particular to a multi-chip offset stacking packaging structure in which a lead frame is provided with multi-section bus bars. Background technique [0002] In recent years, three-dimensional (3D) packaging is being carried out in the post-process of semiconductors, in order to achieve a relatively large integrated semiconductor or memory capacity with the least area. In order to achieve this goal, a chip stacked method has been developed to achieve a three-dimensional (Three Dimension; 3D) package at this stage. [0003] In the known technology, chips are stacked by stacking multiple chips on a substrate, and then using a wire bonding process to connect the multiple chips to the substrate. Figure 1A It is a schematic cross-sectional view of a known stacked chip package structure with the same or similar chip size. Such as Figure 1A As shown, the known stacked chip package ...

AI Technical Summary

Problems solved by technology

However, when the known technology stacks a plurality of chips of different sizes into the stacked chip package structure 10 in the above-mentioned manner, since the size of the chip on the upper layer must be smaller, the stacked chip package structure 10 has a limitation on the number of stacked chips.

[0007] In the above two traditional stacking methods, in addition to Figure 1A The method of using the spacer 130 is likely to cause the disadvantage that the thickness of the stacked chip packaging structure 100 cannot be further reduced and Figure 1B , because the size of the chip on the upper layer must be smaller, this will not only limit the design or use of the chip; but also because the chip design on the stacked chip package structure is increasingly complex, the circuit connection on the chip must be face-to-face. For jumpers or jumpers, there will be problems in the process, such as the production capacity or reliability of the stacked chip package structure may be reduced

Images