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Sound data processing apparatus

A sound data and processing device technology, applied in sound input/output, speech analysis, television, etc., can solve the problems of increased chip size or manufacturing cost, sound interruption, complex processing, etc., and achieve the effect of reducing the processing burden

Inactive Publication Date: 2008-04-30
SANYO ELECTRIC CO LTD +1
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  • Abstract
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  • Claims
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AI Technical Summary

Problems solved by technology

[0011] However, since there is no audio data buffered in FIFO 20 for DAC or FIFO 24 for DIT, the audio will be interrupted. Therefore, it is necessary to supplement audio data as early as possible when an interruption occurs.
Therefore, if DSP12 receives an interrupt signal, it must temporarily suspend decompression processing or decoding processing, etc., making the processing complicated
Additionally, it is possible to delay processing in the DSP12
[0012] In order to prevent this problem, as long as the memory capacity of the DAC FIFO 20 or the DIT FIFO 24 is large, the circuit scale of the audio data processing device 100 will be increased, and the chip size or manufacturing cost will be increased.

Method used

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Embodiment Construction

[0025] (device structure)

[0026] As shown in FIG. 1 , the sound data processing device 200 in the embodiment of the present invention includes an input module 30, a digital signal processing part (DSP) 32, an intermediate buffer module 34, a buffer memory 36, and a digital / analog conversion part (DAC) 38 , FIFO 40 for DAC, digital interface transmitter (DIT) 42 , FIFO 44 for DIT, digital readout control unit 46 and comparator 48 .

[0027] If the input module 30 receives the voice data separated from the TS packet, it will pass it to the DSP32. Audio data is compressed and encoded. The DSP 32 performs decompression processing and decoding processing of audio data. In addition, the DSP 32 outputs the processed audio data to the intermediate buffer module 34 on the condition that the value of the read pointer (read pointer) input from the data read control unit 46 does not match the value of the current write pointer (write pointer). The read pointer and write pointer will ...

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Abstract

A sound data processing apparatus includes a digital signal processor(32) capable of decoding sound data, a buffer memory(36) functioning as a ring buffer for successively storing the decoded sound data, a data reading controller configured to read sound data from the buffer memory, a DAC-FIFO buffer(40) or a DIT-FIFO buffer(44) storing sound data input from the data reading controller, and a digital / analog converter (DAC) (40)or a digital interface transmitter (DIT) (44)that outputs an interrupt signal to the data reading controller(46) when the sound data stored in the DAC-FIFO buffer memory(38) or the DIT-FIFO buffer memory(42) is equal to or less than a predetermined amount. The data reading controller(46) reads sound data from the buffer memory(36) in response to the interrupt signal if a write pointer value is equal to a read pointer value.

Description

technical field [0001] The present invention relates to a sound data processing device used in communication sound data processing. Background technique [0002] In communications such as televisions, a method of compressing and transmitting image data or audio data using an encoding method such as MPEG (Moving Picture Expert Group) is widely used (for example, refer to Patent Document 1, etc.). [0003] In MPEG, elements such as image data, audio data, and character data are communicated as encoded transport stream packets (TS packets). After the receiving device extracts and separates image data, audio data, and character data from the TS packets, each of them is decoded by a decoder. In addition, when outputting the decoded data, it buffers in the buffer memory of a FIFO (First-In First-Out) system, and outputs it sequentially. [0004] FIG. 5 shows the configuration of a conventional audio data processing device 100 . The sound data processing device 100 includes an i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N7/62H04N5/60G06F3/16
CPCG10L19/16
Inventor 铃木章仁
Owner SANYO ELECTRIC CO LTD
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