Single chip multi-processor shared data storage space access method

Abstract

The invention relates to a visit method for sharing data storing space of a single chip multi-processor, which uses the data space sharing of high 128 bytes in each sub-processor for transmission of command and data among the processors, and a sharing data memory interruption (SDMI) is added in each sub-processor, and the SDMI and an arbiter are effectively combined as a visit mechanism of a data sharing memory for solving competition which exists in data exchange among each sub-processor. The visit of an entire single chip multi-processor to the data sharing memory is only judged by the arbiter, and is realized through the style of interruption. The handshaking signal between the arbiter and each sub-processor adopts on-chip style, and the transmission speed is fast, and the resource which is occupied in little, which is convenient for integration and control. Each sub-processor can not only work separately, but also can coordinately work with other processors. Each micro processor is substantially a relatively simple single-thread micro processor, and a plurality of the sub-processors parallel carry out program codes, which have relatively high command level parallelism. The method can be applied to a multi-processor system of MCS-51 command system, and can be applied to other fields of multi-microcontrollers, and multi-microprocessors and the like.

Description

technical field [0001] The invention relates to a method for accessing shared data storage space of single-chip multiprocessors. It can be applied to the multi-processor system of the MCS-51 instruction system, and can also be applied to other fields such as multi-microcontrollers and multi-microprocessors. Background technique [0002] Shared Data Memory (Shared Data Memory) is a section of storage space used by multiprocessors to store shared data. Each subprocessor can read data to be processed from this space, and can also write data that has been specifically processed into this space. segment space. [0003] Single-chip multiprocessors improve program parallelism by integrating multiple microprocessor cores on one chip. Each microprocessor core is essentially a relatively simple single-threaded microprocessor or a relatively simple multi-threaded microprocessor. Multiple such sub-processors execute program codes in parallel and have high instruction-level parallelism...

AI Technical Summary

Problems solved by technology

The disadvantages of the structure of the current single-chip multiprocessor are: the hardware structure is complex; the software changes are relatively large; the speed gap between the processor and the data memory is large

In addition, the on-chip bus structure adopted by the current multi-core structure is not only a bus, but an interconnection system with interface modules, and the AMBA and Avalon buses are not fully disclosed in the true sense.

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