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Wafer level package with die receiving cavity

A technology of crystal grains and concave holes, which is applied in the field of wafer-level packaging structure, and can solve the problems of reducing chip size and so on

Inactive Publication Date: 2008-05-28
ADVANCED CHIP ENG TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It may conflict with the need to reduce chip size

Method used

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  • Wafer level package with die receiving cavity
  • Wafer level package with die receiving cavity
  • Wafer level package with die receiving cavity

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Embodiment Construction

[0015] The present invention discloses a wafer level packaging (WLP) structure utilizing a substrate having predetermined through holes formed therein and recessed holes formed therein. The photosensitive material is coated on the die and the pre-formed substrate. The photosensitive material is preferably formed of elastic material.

[0016] FIG. 1 is a schematic cross-sectional view of a diffused wafer-level package (FO-WLP) according to an embodiment of the present invention. As shown in FIG. 1 , a diffused wafer level packaging (FP-WLP) structure includes a substrate 2 having a die receiving cavity 4 formed therein to receive a die 16 . A plurality of through holes (through hole structures) 6 are formed through the substrate 2 from the upper surface to the lower surface thereof. Conductive material is filled into the through hole 6 for electrical communication. Terminal pads 8 are disposed on the lower surface of the substrate 2 and connected to the through holes 6 with ...

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PUM

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Abstract

The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through hole structure formed there through, wherein a terminal pad is formed under the through hole structure and the substrate includes a conductive trace formed on a lower surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. A re-distribution metal layer (RDL) is formed on the dielectric layer and coupled to the die and the through hole structure. Conductive bumps are coupled to the terminal pad.

Description

technical field [0001] The present invention relates to wafer level packaging (WLP) structures, and more particularly to a carrier plate having a die receiving cavity for receiving a die in WLP. Background technique [0002] In the field of semiconductor devices, the density of devices continues to increase and the size of devices continues to shrink. In order to cope with the above situation, the demand for packaging or interconnection technology in such high-density components is also increasing. Traditionally, solder bump arrays are formed on the surface of the die in the flip-chip attachment method. Solder bump formation may be performed using a solder composite through a solder mask for producing a desired solder bump morphology. The functions of the chip package include power distribution, signal distribution, heat dissipation, protection and support, etc. As semiconductors become more complex, traditional packaging technologies such as lead frame packaging, flexibl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/488H01L23/498H01L23/13H01L21/50H01L21/58H01L21/60
CPCH01L2924/01015H01L2224/18H01L2924/15153H01L2924/01082H01L2224/97H01L2224/32245H01L2924/12041H01L2924/01002H01L2924/09701H01L24/82H01L2924/01029H01L2924/01027H01L2924/014H01L2924/01013H01L2224/32225H01L24/97H01L2924/19043H01L2224/73267H01L2924/01079H01L2924/01068H01L23/5389H01L2924/14H01L2924/01033H01L2924/01006H01L2924/0102H01L2924/01059H01L2924/01078H01L2924/10253H01L2924/01052H01L2924/01075H01L24/18H01L2224/24227H01L2224/92244H01L2924/15311H01L2924/351H01L2224/04105H01L2224/12105H01L24/24H01L2224/82H01L2924/00H01L2224/83H01L23/12
Inventor 杨文焜张瑞贤
Owner ADVANCED CHIP ENG TECH INC