Apparatus and method for memory operations using address-dependent conditions

Abstract

An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and / or reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and / or bit line driver.

Description

technical field [0001] The present invention relates to the field of memory, and in particular to the operation of memory. Background technique [0002] To program a memory cell, the wordline and bitline drivers associated with the memory cell may be driven with the supplied wordline and bitline voltages, respectively. When the voltage across a memory cell is above a threshold voltage, the memory cell is programmed. To read a memory cell, the wordline and bitline drivers associated with the memory cell can be driven with the supplied wordline voltage and bitline voltage, respectively, and the sense (sense) amplifier associated with the memory cell will output The current of the memory cell is compared with a reference current. If the memory cell is programmed, the current will be greater than the reference current; otherwise, the current will be less than the reference current. Write and read errors occur when the resistance along the wordlines and bitlines causes the act...

AI Technical Summary

Problems solved by technology

Write and read errors occur when the resistance along the word and bit lines causes the actual voltage received by the memory cell (and thus the current through it) to decrease

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