Caching data processing method, device and system

Abstract

The invention relates to a cache data processing method which comprises that: data packets entering the same queue are spliced; the spliced data packets are split into a plurality of data units according to the preset particle size; the split data units are stored in a plurality of storages. The invention also relates to a cache data processing unit and a cache data processing system; the method, the device and the system improve the read / write efficiency of the storages, improve the equilibrium of read / write bandwidths among the storages, thereby improving the performance of the system.

Description

technical field [0001] The present invention relates to the technical field of communications, and in particular to a cache data processing method, device and system. Background technique [0002] Packet buffering is one of the essential key technologies in modern communication equipment. Its main function is to provide data packet buffering when traffic is congested, so as to avoid or reduce traffic loss; with the continuous improvement of port speed, high-end communication Parallel packet cache technology to obtain packet cache bandwidth matching the port speed, as shown in Figure 1, which is a schematic structural diagram of the existing cache data processing system, the system is composed of N parallel memories, and the data packets coming in from the port The queue-entry controller distributes to each memory through the storage controller for caching, the control information of the data packet enters the packet queue, and the dequeue scheduler dispatches the control inf...

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Problems solved by technology

[0005] The inventor found in the process of implementing the present invention that the above-mentioned method has at least the following defects. For example, in the first method, for a general-purpose DRAM memory, small-grained storage will cause a reduction in the read-write efficiency of each memory, thereby reducing the effectiveness of the entire packet cache. Bandwidth; for the second method, the implementation of multi-packet dequeue scheduling is more complicated. At the same time, when a larger storage granularity is used to improve the effective bandwidth of each memory, the space efficiency and bandwidth efficiency of the memory will be greatly reduced. When the packets need to be stored in each memory in order, it will also lead to an increase in the write bandwidth imbalance between multiple memories

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