Test carrier plate

A technology for testing carrier boards and test pads, which is applied in electronic circuit testing, single semiconductor device testing, and electrical measurement, etc., can solve problems such as affecting accuracy, disconnection of wire 140, poor reliability, etc., to improve reliability and improve reliability. The effect of accuracy

Active Publication Date: 2010-06-02
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Since the wires 140 of the conventional test carrier 100 are disposed on the surface 112 of the dielectric layer 110, it is easy to be subjected to structural stress concentration or external force after the package component 50 is bonded to the test carrier 100, so that the wires 140 An open circuit is formed in the stress concentration area 150, which will lead to the inability to determine whether the measured error is caused by a poor connection between the package component 50 and the test carrier 100 during testing, or is caused by a disconnection of the test carrier 100 itself. caused by
In other words, this unreliable test carrier design will directly affect the accuracy of the test

Method used

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Embodiment Construction

[0045] Figure 2A It is a top view of the test carrier board in an embodiment of the present invention, Figure 2B for Figure 2A A cross-sectional view of a mid-test carrier carrying a packaged component. Please refer to Figure 2A and Figure 2B , the test carrier 200 can be applied to test a packaged component 50, the test carrier 200 includes a dielectric layer 210, a plurality of pads 220, a pad connection line 232, a plurality of test pads 240 and a plurality of first wires 252 .

[0046] According to the above, the dielectric layer 210 has a first surface 212 and a second surface 214 opposite thereto, and the first surface 212 has a component bonding area 212 a for carrying the package component 50 . The pads 220 are arranged in an array, for example, and are located on the first surface 212 in the device bonding area 212 a for bonding with the package device 50 . The pad connection lines 232 are located on the first surface 212 and electrically connected to the p...

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Abstract

The invention discloses a test board which comprises a component conjugate area for supporting one package element and testing the package element, a plurality of dielectric layers, a surface circuitlayer, at least one inner circuit layer, a plurality of conjugate pads and a plurality of test pads, wherein the surface circuit layer is outside the dielectric layers, the inner circuit layer is between two nearby dielectric layers and electrically connected with the surface circuit layer, the conjugate pads are arranged on the surface circuit layer in the component conjugate area to be conjugated with the package element, the conjugate pads are electrically connected with the surface circuit layer and the inner circuit layer, the test pads are arranged on the surface circuit layer outside the component conjugate area, and the test pads are electrically connected with relative conjugate pads via the inner circuit layers.

Description

technical field [0001] The present invention relates to a test carrier, and more particularly to a test carrier for reliability testing of chip bonding. Background technique [0002] In the manufacturing process of integrated circuits or chips, no matter at which stage of the process, it is necessary to perform electrical tests on integrated circuits or chips. Every integrated circuit, no matter in the form of the wafer or the form of the structure, must be tested to determine whether it is a good product and to determine its electrical characteristics. As the output of integrated circuits continues to increase, the functions of integrated circuits are becoming more powerful, and their structures are becoming more and more complex, so the demand for high-speed and accurate testing is more urgent. [0003] Figure 1A A top view of a known test carrier board, Figure 1B for Figure 1A A cross-sectional view of a mid-test carrier carrying a packaged component. Please refer t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28G01R31/26G01R1/02H01L21/66
Inventor 王静君黄东鸿叶昶麟赖逸少
Owner ADVANCED SEMICON ENG INC
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