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Chip package structure and its package method

A chip packaging structure, chip packaging technology, applied in the direction of electrical components, electrical solid devices, semiconductor/solid device manufacturing, etc., can solve the problems of increased package thickness, improved short circuit, difficult to effectively control the distance, etc.

Inactive Publication Date: 2008-08-06
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, the increase of the length of the wire 150 will not only increase the possibility of short circuit (adjacent wires 150 are in contact) and open circuit, but also the distance between the wire 150 and the upper surface of the chip 140 is difficult to effectively control, which will easily lead to an increase in the thickness of the overall package.

Method used

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  • Chip package structure and its package method
  • Chip package structure and its package method
  • Chip package structure and its package method

Examples

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Embodiment Construction

[0019] 2A to 2F are a series of schematic diagrams of a preferred embodiment of the chip packaging method of the present invention. First, as shown in FIG. 2A , a wiring board 220 is provided. At least one finger 222 is formed on the circuit board 220 . The finger can be used to transmit electrical signals to a circuit board (not shown). Subsequently, as shown in FIGS. 2B and 2C , the first chip 240 is installed on the circuit board 220 . The first chip 240 has at least one pad 242 located at the center of the upper surface of the first chip 240 . As shown in the figure, for a preferred embodiment, two rows of bonding pads 242 may be disposed at the center of the upper surface of the first chip 240 .

[0020] Next, as shown in FIG. 2D , make at least one wire (bonding wire) 250 extending from the pad 242 along the upper surface of the first chip 240 toward the edge of the first chip 240, and electrically connected to the circuit board made Finger 222 on 220 . It should be...

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Abstract

The invention discloses a chip packaging structure and a packaging method thereof. The chip packaging method includes the following steps that: (a) a circuit board is provided and a finger is formed on the circuit board; (b) a first chip which is provided with at least one welding pad on the upper surface is assembled on the circuit board; (3) at least one lead wire which extends from the welding pad to the finger along the upper surface of the first chip and is in electric connection with the finger is formed, and a clearance is left between the lead wire and the upper surface of the first chip; (d) the clearance is filled with the non-conducting resin, forming the connection between the non-conducting resin layer and the lead wire and the upper surface of the first chip, and the distance between the lead wire and the upper surface of the first chip is smaller than the prior clearance between the lead wire and the upper surface of the first chip; and(e) the seal colloid is formed to cover the first chip and the lead wire.

Description

technical field [0001] The invention relates to a chip packaging structure and a packaging method thereof, in particular to a chip packaging structure utilizing wire-bonding and a packaging method thereof. Background technique [0002] Please refer to FIGS. 1A and 1B , which are a schematic cross-sectional view and a schematic top view of a typical wire-bonding chip package structure 10 . As shown in the figure, the chip package structure 10 includes a circuit board 120 , a chip 140 and an encapsulant 160 . The chip 140 is disposed on the circuit board 120 . Soldering pads 142 are formed at the edge of the upper surface of the chip 140 . The pad 142 is electrically connected to the finger 122 on the surface of the circuit board 120 through the wire 150 . The encapsulant 160 covers the chip 140 and the wires 150 to provide protection. [0003] As the density of electronic components in the chip 140 increases, the number of bonding pads 142 must also increase accordingly. ...

Claims

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Application Information

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IPC IPC(8): H01L21/50H01L21/60H01L21/56H01L23/48H01L23/485H01L23/488H01L23/31H01L25/00H01L25/065
CPCH01L24/48H01L2224/4899H01L2924/01082H01L2924/00014H01L2224/48465H01L24/05H01L24/06H01L2224/48227H01L2924/01005H01L2924/01033H01L2224/4809H01L2924/01006H01L2224/48091H01L2224/49175H01L2224/04042H01L2224/05554H01L2224/48H01L2924/181H01L2924/00H01L2224/05556H01L2924/00012H01L2224/48132
Inventor 谢其良林圣惟李哲毓
Owner ADVANCED SEMICON ENG INC
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