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Gate metal routing for transistor with checkerboarded layout

A technology of transistors and gates, applied in the field of semiconductor device structures, can solve problems such as warping and large silicon wafers

Active Publication Date: 2008-08-20
POWER INTEGRATIONS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this layout poses a problem in that the silicon wafer is prone to large warpage during high temperature processing steps

Method used

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  • Gate metal routing for transistor with checkerboarded layout
  • Gate metal routing for transistor with checkerboarded layout
  • Gate metal routing for transistor with checkerboarded layout

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Embodiment Construction

[0021] In the following description, specific details are given, such as material types, dimensions, structural features, processing steps, etc., in order to provide a thorough understanding of the present invention. However, one of ordinary skill in the art will understand that these specific details may not be required to practice the present invention. It should also be understood that the elements in the figures are representative and not drawn to scale for the sake of clarity.

[0022] FIG. 1 shows an example cross-sectional side view of a vertical HVFET 10 having a structure including an extended drain region 12 of N-type silicon formed on an N+ doped silicon substrate 11 . The substrate 11 is heavily doped to minimize its resistance to current flow through the drain electrode, which in the completed device is located on the bottom of the substrate. In one embodiment, the extended drain region 12 is part of an epitaxial layer extending from the substrate 11 to the top s...

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Abstract

The invention relates to a gate metal routing for transistor with checkerboarded layout. In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Description

technical field [0001] The present invention relates to semiconductor device structures and processes for fabricating high voltage transistors. Background technique [0002] High voltage field effect transistors (HVFETs) are well known in the semiconductor art. The device structure employed by many HVFETs includes an extended drain region that supports or blocks applied high voltages (eg, several hundred volts) when the device is in the "off" state. In a conventional vertical HVFET structure, mesas or pillars of semiconductor material form an extended drain or drift region for current in the on-state. A trench gate structure is formed near the top of the substrate adjacent to sidewall regions of the mesa where the body region is disposed over the extended drain region. Application of an appropriate voltage potential to the gate forms a conductive channel along the vertical sidewall portion of the body region so that current can flow vertically through the semiconductor mat...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/41H01L29/423H01L29/417H01L29/06
CPCH01L29/407H01L21/77H01L29/0696H01L29/0878H01L29/41741H01L29/4236H01L29/42372H01L29/4238H01L29/7813
Inventor V·帕塔萨拉蒂
Owner POWER INTEGRATIONS INC