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Device, system and method for testing and analysing integrated circuits

A technology of integrated circuits and connecting devices, applied in the field of testing and analyzing integrated circuits, capable of solving problems such as inappropriate

Inactive Publication Date: 2008-08-20
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The resulting device is a disposable integrated circuit package not suitable for use in product

Method used

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  • Device, system and method for testing and analysing integrated circuits
  • Device, system and method for testing and analysing integrated circuits
  • Device, system and method for testing and analysing integrated circuits

Examples

Experimental program
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Embodiment Construction

[0055] In FIGS. 1 a and 1 b , the basic principle of the invention is explained with reference to a schematic representation of a plan view of a device according to the invention. The device 1 comprises a carrier 5 on two sides A1, A2 of which contacts P1a, P1b, P2, P1a', P1b', P2' are arranged. The carrier 5 can be, for example, a printed circuit board (PCB). In this example, the carrier 5 has a circular shape (not necessary), with a diameter of 8 inches and a thickness of about 3 mm.

[0056] The meaning of a contact should be understood as a terminal to which a test system (not shown) can be connected either via or not via some interface. The test system may also include a tester such as the Agilent 93000. These contacts can be voids or protrusions protruding from the surface, or a combination of both. The contacts P1a, P1b, P2, P1a', P1b', P2' may be signal contacts, but also, for example, power or ground contacts. In the detailed examples of this description, the carr...

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PUM

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Abstract

This invention relates to a semiconductor device for testing and analyzing integrated circuits (1) on a first side and a second side. The semiconductor device (1) having a first surface (A1) and a second surface (A2) both sides having a set of contacts (P3a, P3b, P3a′, P3b′). The sets of contacts on are symmetrically located on positions relative to a first fictitious plane of symmetry (S1) and a second fictitious plane of symmetry (S2). The semiconductor device (1) has at least a first position of use and a second position of use, whereby the second position of use is obtained by rotating the semiconductor device (1) in the first position of use 180° around a fictitious axis (M). This axis (M) is defined by the crossing of the first fictitious plane of symmetry (S1) and the second fictitious plane of symmetry (S2). The semiconductor device thus obtained provides a flexible and generic solution for testing and analyzing integrated circuits on both sides.

Description

technical field [0001] The invention relates to a device for testing and analyzing integrated circuits on a first side and a second side of the device. [0002] The invention also relates to a system for testing and analyzing integrated circuits on a first side and a second side of a device, wherein said system comprises such a device. [0003] The invention further relates to a method for testing and analyzing an integrated circuit on a first side and a second side, wherein a device according to the invention is used. Background technique [0004] A device of this type is known from US patent 6,127,833. This document describes a semiconductor test carrier comprising an insulating substrate having a top surface, a bottom surface and a perimeter; a rectangular cavity centrally located on the top surface and extending through to the bottom surface. At the periphery of the cavity, conductive ground traces are formed on the top surface, conductive corner power traces are forme...

Claims

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Application Information

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IPC IPC(8): G01R31/28
CPCG01R31/2887G01R31/2889
Inventor 安东尼·S·J·格默
Owner NXP BV