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Method for multi-processor to parallel implement high-definition picture filtering

A high-resolution image, multi-processor technology, used in image communication, television, electrical components, etc.

Inactive Publication Date: 2011-06-22
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, when filtering the current macroblock, the data of the above and left macroblocks must be filtered so that the data can be used, which makes it difficult for multi-chip processors to perform parallel calculations.
A simple and feasible method is that the single-chip processor completes the processing of the entire frame of the image. The efficiency achieved in this way undoubtedly wastes the resources of other processors, because other processors cannot perform any other actions before the filtering process is completed.
Another solution is to separate the luminance and chrominance by two digital signal processors (Digital Signal Processing, DSP), but considering that the data volume of luminance is twice that of chrominance (the image format is 4:2:0) , and the computational complexity is almost twice that of chroma, and the total resource overhead is nearly 4:1, so this solution does not make full use of the resources of multi-chip processors

Method used

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  • Method for multi-processor to parallel implement high-definition picture filtering
  • Method for multi-processor to parallel implement high-definition picture filtering
  • Method for multi-processor to parallel implement high-definition picture filtering

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Embodiment Construction

[0024] Combine below figure 2 with image 3 The present invention is further described in detail.

[0025] In the present invention, it is assumed that the number of processors is N, and the number of macroblock rows of an image is M, and the number of macroblocks in each row is L. L may or may not be divisible by N. When L is divisible by N, the number of macroblocks in each share is [L / N]; when L is not divisible by N, the number of macroblocks in the first N-1 shares is [L / N] , and the number of Nth macroblocks is L-(N-1)*[L / N].

[0026] In this embodiment, DSP is taken as an example, and N=4, which are DSP_0, DSP_1, DSP_2 and DSP_3 respectively; and L can be divided by N, that is, it is divided into 4 parts:

[0027] first step

[0028] DSP_0 filters the first 1 / 4 line of the first macroblock line. The reconstruction data after filtering is written in the off-chip memory (the following steps are all stored in the off-chip memory after completion). At this point, DS...

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Abstract

The invention relates to a method for realizing high-definition image filtration through the parallel of multi-processor. The invention adopts the steps that firstly, the macro-blocks in image macro-block rows are divided into shares in the number identical with the number of processors in sequence; then filtration is performed, after filtration to the corresponding shares in the macro-block rowsis completed by the previous processor, subsequent filtering operation to the next share in the macro-block row is performed by the next processor, and filtration to the corresponding share in the next macro-block row is performed by the previous processor, followed by analogy, until the completion of the filtration of a frame. Through the method, dada in a macro-block row is divided into shares in the number identical with the number of the processors by utilizing characteristics of large data volume of video with high definition format, each processor is in charge of computation to pixel filtration of different rows, previously, the previous filtration ensures data both at the upper side and the left side to be available and the parallel computation to be smoothly performed. Through themethod, filtration and computation can be simultaneously performed by almost all the processors, thereby the resource of the multi-processor is effectively utilized, and the processing efficiency is enhanced.

Description

technical field [0001] The invention belongs to the field of image information compression, in particular to a method for parallel realization of high-resolution image coding (or decoding) filtering on multi-chip processors. Background technique [0002] The MPEG-4 PART-10 AVC proposal, that is, the H.264 standard, has won the favor of the industry for its superior video image compression efficiency and reconstructed image quality. However, the high definition of H.264 is at the cost of space and time complexity. Under the same video coding conditions, the time required for H.264 coding is more than three times that of H.263, and H.264 Larger memory space is required to store huge intermediate data. Therefore, when using H264 to encode (or decode, without loss of generality, the following unified encoding) for high-resolution images (such as D1, 720p, 1080i), today's single processors such as DSP, ARM, or It is very difficult for FPGA to support real-time encoding, especia...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N7/26H04N19/117
Inventor 陈晨航梁立伟王宁
Owner ZTE CORP