Path delay fault simulation method and apparatus

Abstract

The embodiment of the invention discloses a simulation method and a device of path delay faults, wherein, firstly, while a circuit topology of a test circuit and a fault set consisting of testabilitypath delay faults in the test circuit are input, a test vector set consisting of test vectors corresponding to all the path delay faults in the fault set is input; according to the paths correspondingto all the path delay faults in the fault set, a path choice circuit is constructed; the path choice circuit is an equivalent circuit of the paths with the path delay faults in the test circuit; according to all the test vectors in the test vector set, backward fault simulation is carried out in the test circuit, and according to the path delay faults obtained from the simulation, the path choicecircuit is pruned. The proposal provided by the embodiment of the invention can provide an accurate simulation result of the path delay faults in short time; therefore, the proposal provides a reliable simulation method of the path delay fault for chip test.

Description

technical field [0001] The invention relates to the technical field of integrated circuit fault simulation, in particular to a path delay fault simulation method and device. Background technique [0002] After the integrated circuit chip is packaged, the quality of the chip needs to be tested. Since the internal circuit of the chip cannot be directly accessed after the chip is packaged, the general method for testing the chip is: inserting test vectors at the input end of the chip, and collecting test responses at the output end of the chip. The actual test response obtained is compared with the test response obtained by the fault-free circuit, so as to determine whether the chip circuit is faulty or not. A test vector refers to a set of logic values ​​placed into the internal circuit through the chip input. [0003] In order to study the problem, it is usually necessary to abstract the physical defect in the actual chip into a logical fault model. The commonly used fault...

AI Technical Summary

Problems solved by technology

[0019] Embodiments of the present invention provide a path delay fault simulation method and device, which are used to increase the speed of fault simulation and solve the problems of low efficiency and low accuracy existing in the path delay fault simulation process in the prior art

Images