Multi-speed ring oscillator

Abstract

An annular oscillator comprises a control circuit for receiving the frequency selecting signal; the frequency selecting signal can be operated as processing the selection in at least two different annular oscillator frequencies; the control circuit uses the control signal to generate a first control signal and a second control signal; a main chain with the odd number series-connecting connections, the main chain comprises a main switch non-gate; the main switch non-gate is responding to the first control signal which can be operated as implementing the logical non-function or ignoring function for the first oscillating inputting signal to output the first outputting signal; and a slave chain series-connecting non-gate; the slave chain is collaterally connected to the main switch non-gate of the main china at least; the slave chain comprises a slave switch non-gate; the slave switch non-gate is responding to the second control signal which can be operated as implementing the logical non-function or ignoring function for the second oscillating inputting signal to output the second outputting signal.

Description

technical field [0001] This invention relates generally to digital circuits and, more particularly, to multispeed ring oscillators. Background technique [0002] A ring oscillator is a device that includes an odd number of NOT gates, such as an inverter whose output voltage oscillates between logic high and logic low. The NOT gates of the traditional ring oscillator are connected in a circular chain, so that the output voltage of the last NOT gate among the odd number of NOT gates is fed back as the input of the first NOT gate. Since the chain includes an odd number of NOT gates, the logic voltage leaving the last NOT gate is the logical NOT of the input voltage previously entering the first NOT gate. Therefore, the output voltage of each NOT gate in the loop oscillates. Since the output voltage of the last NOT gate is judged to reach the first NOT gate a finite amount of time after the previous input voltage, each NOT gate oscillates at a predictable frequency. [0003] ...

AI Technical Summary

Problems solved by technology

[0006] In current semiconductor technology for embedded CMOS microprocessor systems, the ability to use EDA tools for ring oscillator design and layout is desirable because embedded CMOS microprocessor systems use small linewidths, such as 130nm and 45nm, which In this case the interstage routing delay due to parasitic capacitance becomes significant and may exceed the gate delay of the inverter

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