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Fast fourier transform circuit, processor and method and OFDM receiver

A technology of Fourier transform and stage circuit, applied in the field of FFT, which can solve the problems of area, delay and energy consumption burden

Inactive Publication Date: 2012-01-11
OPTIS WIRELESS TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0014] Given the above discussion, it is clear that state-of-the-art approaches face significant burdens in area, latency, and energy consumption

Method used

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  • Fast fourier transform circuit, processor and method and OFDM receiver
  • Fast fourier transform circuit, processor and method and OFDM receiver
  • Fast fourier transform circuit, processor and method and OFDM receiver

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Embodiment Construction

[0032] The various features of the invention will now be described with reference to the drawings, in which like reference numerals are used to designate like parts.

[0033]Various aspects of the invention will now be described in more detail in connection with a number of exemplary embodiments. To facilitate an understanding of the invention, many aspects of the invention are described in terms of sequences of actions to be performed by elements of a computer system or other hardware capable of executing programmed instructions. It should be appreciated that, in each of the embodiments, the various actions may be implemented by dedicated circuitry (e.g., discrete logic gates interconnected to perform the dedicated functions), by program instructions executed by one or more processors, or by both. combination of operators to perform. Furthermore, the present invention may also be considered embodied in any form of computer-readable carrier, such as solid-state memory, magnet...

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Abstract

A Decimation In Frequency Fast Fourier Transform (DIF FFT) stage is used in an N bin FFT, wherein N is an even integer. The DIF FFT stage includes swap logic that receives a first input sample x (v), and a second input sample x (v+N / 2), and selectively supplies either the first and second input samples at respective first and second swap logic output ports or alternatively the second and first input samples at the respective first and second swap logic output ports, wherein 0<=v<N / 2; a summing unit for adding values supplied by the first and second swap logic output ports; a differencing unit for subtracting values supplied by the first and second swap logic output ports; and twiddle factor logic that multiplies a value supplied by the differencing unit by a twiddle factor, WN< (v+s) mod (N / 2)>, where s is an integer representing an amount of circular shift of N input samples.

Description

technical field [0001] The present invention relates generally to the Fast Fourier Transform (FFT), and more particularly to implementing the FFT with a cyclic shift of input data or equivalently with a rotation of each output data. Background technique [0002] FFTs have numerous applications in modern digital signal processing, from low-level telecommunication signaling to speech and image processing. In some applications, the transformed data set is pre-shifted or post-rotated for specific purposes. [0003] From transformation theory we know that front shift and back rotation are equivalent operations. However, in conventional arrangements, their implementation differs from each other. The front shifter consists of a buffer at least the size of the transform and some addressing logic. In contrast, the post-rotator is implemented as a complex multiplier or as a pure rotator eg using a Coordinate Rotation Digital Computer (CORDIC) algorithm and some kind of rotation ang...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L27/26G06F17/14
CPCH04L27/265G06F17/142H04L27/2662H04L27/2651H04L27/26
Inventor 利夫·威廉松吉姆·斯文森安德斯·贝尔克曼
Owner OPTIS WIRELESS TECH LLC