Electrostatic discharging protection circuit

Abstract

The invention relates to an electrostatic discharge protection circuit which comprises a first terminal (VDD) and a second terminal (VM), and is characterized by further comprising a parasitic field effect transistor; a grid electrode and a drain electrode of the parasitic field effect transistor are connected, a source electrode and a substrate of the parasitic field effect transistor are connected, and the parasitic field effect transistor is connected between the first terminal and the second terminal; when the second terminal has positive electrostatic pulse voltage relative to the first terminal, static is discharged by positively conducting the drain electrode of the parasitic field effect transistor to a parasitic diode of the substrate of the parasitic field effect transistor; whenthe absolute value of the negative electrostatic pulse voltage of the second terminal relative to the first terminal is greater than the conduction threshold value of the parasitic field effect transistor, the static is discharged by conducting the parasitic field effect transistor.

Description

technical field [0001] The invention relates to an electrostatic discharge protection circuit, in particular to a circuit for electrostatic discharge protection of high voltage pins and negative voltage pins. Background technique [0002] ESD protection is very important for integrated circuits, and a lot of research has been done in the industry. Electrostatic discharge may occur in the normal use of electronic equipment, transportation and storage, as well as in the production and assembly of various integrated circuit components. These electrostatic discharges, which are difficult to predict and prevent correctly, can damage integrated circuits, generate defective rates, and even lead to huge losses. In the design and manufacture of current integrated circuits, special attention will be paid to the design of electrostatic discharge protection circuits. The ESD protection circuit is usually connected between two different pins in parallel with the internal circuit. As t...

AI Technical Summary

Problems solved by technology

The diode’s reverse current discharge ability is very poor. Generally, even if a very large chip area is used in the design, it is still difficult to obtain a good discharge effect.

The activation voltage of the high-voltage PMOS shown is lower than that of the diode, but its current discharge capability after breakdown is still not ideal, and it is difficult to trigger the parasitic PNP like the NMOS triggers the parasitic NPN in the general low-voltage electrostatic protection

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