Multi-processor circuit with shared memory banks

Abstract

A plurality of processors (10) in a multiprocessor circuit is coupled to a plurality of independently addressable memory banks (12) via a connection circuit (14). The connection circuit is arranged to forward addresses from a combination of the processors (10) to addressing inputs of memory banks (12) selected by the addresses. The connection circuit (14) provides for a conflict resolution scheme wherein at least one of the processors (10) is associated with an associated one of the memory banks (12) as an associated processor. The connection circuit (14) guarantees the associated processor a higher minimum guaranteed access frequency to said associated one of the memory banks (12) than to a further one of the memory banks (12) other than the associated one of the memory banks (12). A defragmenter (16) detects data associated with a task running on the associated processor (10) that is stored on the further one of the memory banks (12) and move said data to the associated one of the memory banks (12) during execution of the task. The defragmenter causes addressing of the data by the associated processor (10) to be remapped from said further one of the memory banks (12) to the associated one of the banks after said moving, preferably incrementally as movement of data progresses.

Description

technical field [0001] The present invention relates to multiprocessor circuits. Background technique [0002] Memory access conflicts arise from problems with multiprocessor circuits. In a simple multiprocessor system, each processor is provided with its own memory bank that only it can access. Thus, no access conflicts will occur, however, the memory banks must be sized to support the most demanding tasks, implying considerable overhead for other tasks. Also, inter-processor communication cannot be performed through memory banks because these memory banks are only accessible to a single processor. [0003] An alternative is to use shared memory for all processors. However, this slows down multiprocessor systems in case of access conflicts. This problem can be alleviated by providing cache memories, where each cache memory is located between a respective processor and main memory. However, the cache memory greatly reduces the worst-case performance of the system (long ...

AI Technical Summary

Problems solved by technology

The use of caches also complicates memory design when compatibility between different caches must be maintained

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