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Method and system for high power switching

A technology of field effect transistors and gates, which is applied in the field of signal processing, and can solve problems such as high cost, increased switch insertion loss, and large circuit size

Inactive Publication Date: 2009-02-18
RAYTHEON CO
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

One problem with this approach is that the large number of switching FETs stacked in series makes the circuit large and therefore expensive
And it will also increase the insertion loss of the switch (insertion loss)

Method used

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  • Method and system for high power switching
  • Method and system for high power switching
  • Method and system for high power switching

Examples

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Embodiment Construction

[0011] By referring to Figure 1 of the accompanying drawings to Figure 3B , to better understand the exemplary embodiments of the present invention and advantages thereof, like reference numerals are used in the various drawings to indicate like and corresponding parts.

[0012] FIG. 1 is a schematic diagram illustrating a conventional high power switch 10 . Switch 10 includes antenna node 12 , first leg 14 , second leg 16 , and output nodes 22 and 24 . The first leg 14 includes a plurality of field effect transistors (FETs) 18 stacked in series. The second leg 16 includes a plurality of FETs 20 stacked in series.

[0013] In operation, a radio frequency or alternating current signal is received by antenna 12 and the received signal is switched to either output 22 or output 24 . This switching is accomplished by either all FETs 18 or all FETs 20 on the respective paths 14 and 16 being on or off together. In certain implementations, such as cellular telephones, the control...

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PUM

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Abstract

According to one embodiment of the invention a method for switching an alternating current signal between at least two paths includes providing, in at least one of the paths, first and second field effect transistors in series. The method also includes providing a control voltage node operable to receive a control voltage and maintaining each of the first and second field effect transistors in pinch-off mode by offsetting a voltage on each gate of the field effect transistors with a DC voltage component other than the control voltage when it is desired for the alternating current not to flow through the at least one path.

Description

technical field [0001] The present invention relates generally to signal processing, and more particularly to methods and systems for high power switching. Background technique [0002] In terms of power handling, a switching field effect transistor (FET) is limited in its high impedance "off" state by the gate bias voltage used to control the device. In the high impedance state, the switching FET is usually connected to an amplifier which is also biased off and has the effect of putting the switching FET in a shunt configuration with the source terminated by a short circuit. For most switching FETs, the gate terminal is "open" terminated with an RF. Therefore, approximately half of the RF voltage on the drain appears on the gate and is superimposed on the gate bias. The RF voltage swing across the switching FET turns the FET “on” for a portion of the RF cycle, thereby reducing power handling if one of the following conditions occurs: (1) The RF voltage swing on the gate e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/10H03K17/687H03K17/693H04B1/48
CPCH03K17/693Y10T307/845H03K17/6871Y10T307/858H03K17/102H03K17/10H03K17/687
Inventor 大卫·D·黑斯顿乔恩·E·穆尼
Owner RAYTHEON CO
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