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Semiconductor chip and semiconductor device having a plurality of semiconductor chips

A semiconductor and chip technology, applied in semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve the problem of waste of chip area

Inactive Publication Date: 2012-07-18
LAPIS SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, according to the technology described in Patent Document 1, when the semiconductor chip is used alone, the pads and the protection circuit become unnecessary structures, resulting in a waste of chip area.

Method used

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  • Semiconductor chip and semiconductor device having a plurality of semiconductor chips
  • Semiconductor chip and semiconductor device having a plurality of semiconductor chips
  • Semiconductor chip and semiconductor device having a plurality of semiconductor chips

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0026] According to the first embodiment of the present invention, electrode pads are provided in corner regions of the outer periphery of the semiconductor chip, and electrostatic discharge (ESD) protection circuits are provided in the corner regions of the semiconductor chip. The ESD protection circuit is electrically connected to the electrode pad and the ground bus of the semiconductor chip.

[0027] use Figure 1 to Figure 5 A semiconductor device according to a first embodiment of the present invention will be described.

[0028] figure 1 It is a perspective view showing a schematic configuration of the semiconductor device according to the first embodiment. figure 2 It is a figure which shows the electrical connection relationship of the characteristic part of the semiconductor device of 1st Embodiment. image 3 It is a plan view showing the structure of the characteristic part of the semiconductor device of the first embodiment. Figure 4 It is a plan view illustr...

no. 2 Embodiment approach

[0080] Next, a second embodiment of the present invention will be described.

[0081] In the second embodiment of the present invention, a second ESD protection circuit is added to the corner region of the semiconductor chip. The second ESD protection circuit is electrically connected between the electrode pads and the power bus of the semiconductor chip.

[0082] use Figure 6 ~ Figure 8 A semiconductor device according to a second embodiment of the present invention will be described.

[0083] Image 6 It is a figure which shows the electrical connection relationship of the characteristic part of the semiconductor device of 2nd Embodiment. Figure 7 It is a plan view showing the structure of the characteristic part of the semiconductor device of the second embodiment. Figure 8 It is a diagram illustrating a specific configuration example of an ESD protection circuit that can be used in the semiconductor device of the second embodiment.

[0084] The schematic structure ...

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Abstract

The present invention comprises a semiconductor chip, and a semiconductor device having a plurality of semiconductor chips, that enables ESD protection from another semiconductor chip without increasing the chip area in case the semiconductor chip is Multi-Chip-Packaged, without wasting chip area in case the semiconductor chip is not Multi-Chip-Packaged. The exemplary semiconductor chip 1 of the present invention includes an internal circuit 28 and a first electrode pad 10 electrically connected to a ground bus line 36 of the first semiconductor chip 1 in a region where an electrode pad, which gives and receives electric signals required for an operation of the internal circuit 28, cannot be provided.

Description

technical field [0001] The present invention relates to a semiconductor chip that prevents electrostatic breakdown between a plurality of semiconductor chips, and a semiconductor device that mounts the semiconductor chip that prevents electrostatic breakdown between a plurality of semiconductor chips and other semiconductor chips. Background technique [0002] In recent years, a multi-chip package (Multi Chip Package: hereinafter sometimes referred to as MCP) technology in which a plurality of semiconductor chips is packaged into one package has become widespread. [0003] In addition, in order to protect a plurality of semiconductor chips that are MCPized from the influence of electrostatic discharge (Electrostatic Discharge: hereinafter sometimes referred to as ESD) between them, it is proposed to connect the ground bus line of one semiconductor chip to the other semiconductor chip through a protection circuit. The technology of the ground bus electrical connection (refer ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/50H01L23/528H01L25/00H01L23/488H01L23/60
CPCH01L25/065H01L23/50H01L23/60H01L2224/48227H01L2924/13091H01L2924/00
Inventor 加藤且宏
Owner LAPIS SEMICON CO LTD