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High-frequency clock detection circuit

A high-speed clock and detection circuit technology, applied in frequency measurement devices, electrical digital data processing, instruments, etc., can solve problems such as clock signal period limitation

Inactive Publication Date: 2009-05-06
LAPIS SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, in the technique disclosed in Patent Document 1, there is a problem that the period of the clock signal to be detected is limited.

Method used

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no. 1 Embodiment

[0022] FIG. 2 shows a first embodiment of the present invention, showing the configuration of a high-speed clock detection circuit. The high-speed clock detection circuit 100 is roughly divided into three circuit sections, and is composed of a normal loop return circuit section 20 , a delay loop return circuit section 30 , and a detection result output circuit section 10 .

[0023] The common loop return circuit part 20 includes a D (delay) type flip-flop circuit 21 and an inversion circuit 22, the output signal (F / F-1 value) of the flip-flop circuit 21 is inverted by the inversion circuit 22, and the obtained inverse The transfer signal is simply looped back and fed back to the trigger circuit 21 as a common looped back signal. In addition, a CPU clock signal input from the outside is supplied to the clock terminal of the flip-flop circuit 21 .

[0024] The delay loop return circuit section 30 includes a D (delay) type flip-flop circuit 31 and an inversion circuit 32 and a d...

Embodiment 2

[0039] Fig. 5 shows a second embodiment of the present invention, showing the configuration of a high-speed clock detection circuit. The high-speed clock detection circuit 100 is composed of a normal loop return circuit section 20 , a delay loop return circuit section 30 , and a detection result output circuit section 10 . The normal loop return circuit unit 20 and the delay loop return circuit unit 30 in the second embodiment have the same configuration as those in the first embodiment.

[0040] In the second embodiment, the configuration of the detection result output circuit unit 10 is different from that of the first embodiment. The detection result output circuit unit 10 includes an exclusive OR circuit 12 and a counter 14 which can be realized by a plurality of flip-flop circuits. The exclusive OR circuit 12 inputs an exclusive OR value (EX-OR value) of the inverted signal from the normal loop return circuit section 20 and the inverted signal from the delay loop return ...

Embodiment 3

[0046] Fig. 7 shows a third embodiment of the present invention, showing the configuration of a high-speed clock detection circuit. The high-speed clock detection circuit 100 is composed of a normal loop return circuit unit 20 , a delay loop return circuit unit 30 and a detection result output circuit unit 10 , and also includes a count threshold setting register 41 and a bus interface 42 . The normal loop return circuit unit 20 and the delay loop return circuit unit 30 in the third embodiment have the same configuration as those in the first and second embodiments.

[0047] The detection result output circuit unit 10 in the third embodiment has the function of changing the count threshold by referring to the count threshold setting register 41 in addition to the configuration in the second embodiment. The content of the count threshold setting register 41 is set by executing software in the control circuit (see FIG. 2 ) via the bus interface 42 . The counter 14 outputs a hig...

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PUM

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Abstract

In order to provide a high frequency clock detection circuit capable to detect a high frequency clock using any period as a threshold, the high frequency clock detection circuit of the present invention includes a delay circuit having a delay time set to be longer than a clock period corresponding to the irregular high frequency state, a first flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the first flip-flop circuit, a second flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the second flip-flop circuit through the delay circuit, and a detection-result output circuit for detecting a difference between the output signal from the first flip-flop circuit and the output signal from the second flip-flop circuit and for providing the function circuit with the high frequency clock detection signal indicating the irregular high frequency state corresponding to an occurrence of the difference.

Description

technical field [0001] The present invention relates to a high-speed clock detection circuit which is provided in a circuit device such as an LSI operating according to a clock frequency, and which detects an abnormality in which the clock frequency becomes high. Background technique [0002] High security is required in devices such as settlement terminals used in financial systems. LSIs used in such devices are in danger of being hacked by illegally changing data or stealing data due to attacks from inside and outside the enterprise. There are various methods of attacking the LSI, but one of the methods is to intentionally speed up the external clock of the LSI to cause a CPU installed in the LSI to malfunction. Therefore, against such an attack, a clock detection circuit that detects a clock frequency other than a predetermined frequency is required in order to prevent the LSI from malfunctioning. [0003] figure 1 The outline of an example of a conventional clock dete...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/02
CPCG06F1/04G01R23/02
Inventor 山田健太
Owner LAPIS SEMICON CO LTD
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