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Hardware architecture for decoding FEC of DMB-T demodulation chip and decoding method

A forward error correction decoding and DMB-T technology, which is applied in the field of digital TV terrestrial broadcasting transmission system, can solve the problems of high design complexity and high hardware cost, and achieve the goal of increasing the number of iterations, reducing design costs, and reducing control logic Effect

Active Publication Date: 2010-12-22
MAXSCEND MICROELECTRONICS CO LTD
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Problems solved by technology

Compared with the Min-Sum algorithm, the SPA algorithm has better error correction performance, but its design complexity is higher and requires a higher hardware cost

Method used

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  • Hardware architecture for decoding FEC of DMB-T demodulation chip and decoding method
  • Hardware architecture for decoding FEC of DMB-T demodulation chip and decoding method
  • Hardware architecture for decoding FEC of DMB-T demodulation chip and decoding method

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Embodiment Construction

[0034] Since the error correction performance of FEC is proportional to the number of iterations of LDPC, the maximum number of iterations of LDPC that can be realized by the hardware structure determines the performance characteristics of the hardware structure. Under the performance requirements of DMB-T, the present invention selects SPA algorithm to perform LDPC iteration, and adopts the structure of 8 FEC data processing modules to process data in parallel. Because BCH verification and BCH correction are carried out in the process of LDPC iteration, LDPC The parallel structure of BCH determines the parallel structure of BCH.

[0035] In order to save the LDPC iteration time occupied by BCH verification and BCH correction, in each FEC data processing module, a pipeline structure of LDPC iteration, BCH verification, BCH correction and forward error correction data output is used (see figure 2). Therefore, the entire time of the frame interval can be fully used for the LDP...

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Abstract

The invention discloses a hardware architecture and a decoding method for forward error correction (FEC) decoding in a DMB-T modem chip. The hardware architecture comprises 8 parallel FEC data processing modules, each of which comprises an LDPC data processing module and a BCH data processing module; an input data serial / parallel conversion module is used for receiving input data; the LDPC data processing module is used for realizing the iterative computation during LDPC decoding; an LDPC state controlling module is used for controlling computation enable of the LDPC data processing module and the controlling enable of an LDPC_SRAM memorizer; the BCH data processing module is used for realizing BCH verification and BCH correction; and a BCH state controlling module controls the computation enable of the BCH data processing module and the controlling enable of the BCH SRAM memorizer. The method can efficiently decrease the complexity of realizing the hardware of forward error correction, and improve the forward error correction performance. The invention is applicable to all systems needing LDPC encoding, in particular modem chips of DMB-T digital terrestrial broadcasting.

Description

technical field [0001] The invention relates to a digital television terrestrial broadcast transmission system, in particular to a hardware architecture for forward error correction (FEC) decoding of a DMB-T demodulation chip; the invention also relates to using the hardware architecture to perform forward error correction Decoding method. Background technique [0002] Terrestrial digital broadcasting has been a hot spot in the wireless field in recent years. Since August 1, 2007, my country has implemented a mandatory standard for digital TV terrestrial broadcasting transmission system - national standard DMB-T. The forward error correction coding in the DMB-T system refers to a channel coding technique that introduces data redundancy at the transmitting end, thereby obtaining a certain error correction capability at the receiving end. Forward error correction coding is implemented by concatenating an outer code (BCH code) and an inner code (LDPC code). BCH code is a wid...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N7/64H04N19/89
Inventor 王晶奚肇卿潘国振
Owner MAXSCEND MICROELECTRONICS CO LTD
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