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Dual purpose serializer/de-serializer and method thereof

A deserializer and configuration register technology, applied in parallel/serial conversion, receiver initialization, data exchange through path configuration, etc., can solve problems such as serial/deserializer design limitations

Active Publication Date: 2009-06-03
AVAGO TECH INT SALES PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the time requirements for achieving lock become stricter, the design of the serializer / deserializer in the OLT will face stricter constraints

Method used

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  • Dual purpose serializer/de-serializer and method thereof
  • Dual purpose serializer/de-serializer and method thereof
  • Dual purpose serializer/de-serializer and method thereof

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Embodiment Construction

[0041] Several specific embodiments of the present invention are discussed in detail below. When describing specific embodiments, it should be understood that this is only for describing the present invention. Under the enlightenment of the present invention, those skilled in the art can also make many forms without departing from the gist of the present invention and the scope protected by the claims, and these all belong to the protection scope of the present invention.

[0042] SerDes enable fast and reliable data transfer between physical locations. Here, data that exists in the form of a parallel bus is serialized into a single high-speed signal. In addition to being used in point-to-point systems, serializers / deserializers can also be used in point-to-multipoint systems.

[0043] figure 2It is a schematic diagram of a point-to-multipoint communication network. As shown, the point-to-multipoint network includes a single OLT 210 communicatively connected to a pluralit...

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Abstract

The present invention relates to a dual purpose serializer / de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics.

Description

technical field [0001] The present invention relates to serial / deserializers (SerDes), and more particularly, to a dual-function SerDes for point-to-point and point-to-multipoint communications. Background technique [0002] The serial / deserializer is essentially an integrated circuit (IC or chip) transceiver, which can realize mutual conversion between parallel data and serial data. Wherein, the sending unit outputs a serial data stream after inputting parallel data lines. The transmit unit may also contain a phase-locked loop (PLL) that multiplies the incoming parallel clock to match the serial frequency. For example, a SerDes in a Gigabit Ethernet system has 10 parallel data lines clocked at 125MHz and an output serial data stream clocked at 1.25GHz. Gigabit Ethernet serial / deserializers generally use 8B / 10B encoding schemes to map 8-bit symbols to 10-bit symbols to achieve DC balance on the line. The receiving unit is the reverse process of the sending unit, that is, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04B10/12H04L29/06
CPCH03M9/00H04L7/0004H04J3/0691H04J3/0685H04J3/0697H04L7/00H04L12/28H04B10/2581
Inventor 韦尔·威廉·戴博
Owner AVAGO TECH INT SALES PTE LTD