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Semiconductor device

A semiconductor and device technology, applied in the field of semiconductor devices, to achieve the effect of reducing warpage

Inactive Publication Date: 2011-04-20
SUMITOMO BAKELITE CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the electronic component substrate including the semiconductor package on which is placed also becomes highly miniaturized

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

Experimental program
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Effect test

no. 1 example

[0179] A semiconductor device having substantially the same structure as that of the above-described embodiment is manufactured. Meanwhile, although in the embodiment described above, the solder bumps are provided on the rear surface of the first substrate, in the first embodiment, a terminal is provided for detecting connecting resistance between the substrates.

[0180] The first substrate and the second substrate consist of the same layer structure and layer material. In particular, the first and second substrates are provided with a stack (thickness of approximately 36 microns) alternately provided with three insulating layers and four conductor interconnect layers, and a core layer (thickness 45 microns).

[0181] In Table 1, the resin composition of the insulating layer used for the lamination of the first substrate and the second substrate is shown. In addition, the resin composition of the insulating layer used for the core layer of the first substrate and the second ...

no. 2 example

[0197] The composition of the insulating layer of the laminate is as follows, and other aspects are the same as those of the first embodiment.

[0198] Table 2

[0199] resin

[0200]

no. 3 example

[0202] The composition of the insulating layer of the core layer is as follows, and other aspects are the same as those of the first embodiment.

[0203] The average thermal expansion coefficient of the insulating layer of the core layer in the temperature range from 25°C to its glass transition temperature along the in-plane direction of the substrate is 8ppm / °C, and in the temperature range from 25°C to its glass transition temperature along the thickness direction of the substrate The average coefficient of thermal expansion is 12 ppm / °C.

[0204] table 3

[0205] resin

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Abstract

The present invention discloses a semiconductor device (1) comprising a first substrate (3) on which a first semiconductor chip (2) is mounted, a second substrate (5) on which a second semiconductor chip (4) is mounted, and a connecting section (6) for electrically connecting the first substrate (3) and the second substrate (5). The first substrate (3) comprises buildup layers (31A, 31B) wherein an insulating layer (311) containing a resin and conductor wiring layers (312, 313) are alternately arranged and the conductor wiring layers (312) are connected through a conductor layer (314) formed in a via hole in the insulating layer (311). The second substrate (5) also has the buildup layers (31A, 31B). At least one insulating layer (311) of the buildup layers of at least one of the first substrate (3) and the second substrate (5) has an average linear expansion coefficient in the in-plane direction of the substrate of not more than 35 ppm / DEG C and an average linear expansion coefficient in the substrate thickness direction of not more than 35 ppm / DEG C within the temperature range from 25 DEG C to the glass transition temperature.

Description

technical field [0001] The present invention relates to a semiconductor device, particularly a semiconductor device on which a plurality of semiconductor chips are stacked. Background technique [0002] With the demand for electrical devices with more advanced functions, lighter weight, and more complex structures in recent years, dense integration of electronic components and dense mounting of electronic components are being pursued. Accordingly, electronic component substrates including semiconductor packages disposed thereon also become highly miniaturized. [0003] As a semiconductor device realizing high-density mounting, a semiconductor device having a package-on-package (POP) structure in which a first semiconductor chip is mounted on a substrate and a second semiconductor chip is mounted on the first semiconductor chip has been proposed (Patent Document 1 ). [0004] [Patent Document 1] [0005] Japanese Patent Application Laid-Open No. H07-183426 Contents of th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/065H01L25/07H01L25/18
CPCH01L25/105H01L2924/15331H01L24/48H01L2224/32225H01L2924/01079H01L23/145H01L2924/01004H01L2224/48091H01L2224/48227H01L2224/73265H01L2225/1058H01L2225/1023H01L2224/45139H01L2224/16H01L2224/73204H01L2224/32145H01L2924/01078H01L2224/73203H01L2924/01019H01L2224/16225H01L2924/3511H01L23/3737H01L23/3735H01L2924/30107H01L24/45H01L24/73H01L2924/00011H01L2924/00014H01L2924/12042H01L2924/15311H01L2924/181H01L2924/00012H01L2924/00H01L2224/45099H01L2924/01049H01L2224/45015H01L2924/207H01L23/12H01L25/065H01L25/07H01L25/18
Inventor 杉野光生桂山悟山下浩行
Owner SUMITOMO BAKELITE CO LTD