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Process for manufacturing power semiconductor devices and corresponding power semiconductor devices

A technology for power semiconductors and semiconductors, which is applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., and can solve the problems of unsatisfactory technical solutions, residues, and uneven space charge distribution.

Active Publication Date: 2012-02-08
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Overall, the described technical solutions for obtaining power devices with charge-balancing structures are unsatisfactory, either in terms of their manufacturing cost and complexity, or in terms of achieving a true charge balance (e.g. due to insufficient space charge distribution uniform or due to the presence of residual defects)

Method used

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  • Process for manufacturing power semiconductor devices and corresponding power semiconductor devices
  • Process for manufacturing power semiconductor devices and corresponding power semiconductor devices
  • Process for manufacturing power semiconductor devices and corresponding power semiconductor devices

Examples

Experimental program
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Embodiment Construction

[0017] figure 1 Shows a wafer 1 of semiconductor material, typically silicon, comprising a substrate 2 of a first conductivity type, for example N with a resistivity lower than 10 Ω·cm ++ type, and an epitaxial layer 3 also having a first conductivity type, for example N-type with a resistivity between 0.1Ω·cm and 2Ω·cm. The surface orientation of the wafer 1 is eg , and the epitaxial layer 3 has an upper surface 4 . In order to form the surface implant layer 5 in the vicinity of the upper surface 4 of the epitaxial layer 3, a maskless implementation is performed on the entire wafer with low energy (50-100keV) and an implant dose between 1011 and 10 13 atom / cm 2 N-type injection.

[0018] then( figure 2 ), a plurality of columnar structures 6 are formed in the epitaxial layer 3 for charge balance. As detailed in the co-pending patent application filed in the applicant's name on April 11, 2006, the process for forming the columnar structures 6 involves first performing a...

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PUM

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Abstract

An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.

Description

technical field [0001] The invention relates to a process for manufacturing a power semiconductor device with charge-balancing columnar structures on a non-planar surface, and to a corresponding power semiconductor device. In particular, without implying any lack of generality, the subsequent processing relates explicitly to the fabrication of power MOS devices. Background technique [0002] As we all know, in recent years, in order to improve the efficiency of power semiconductor devices, many technical solutions have been developed, especially in terms of improving breakdown voltage and reducing output resistance. [0003] For example, U.S. Patents 6,586,798, 6,228,719, 6,300,171 and 6,404,010, all filed in the applicant's name, describe vertical conduction power semiconductor devices in which, within an epitaxial layer forming part of a drain region of a given conductivity type, A columnar structure of opposite conductivity type is formed. In these columnar structures, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L21/324H01L29/78H01L29/10H01L21/336H01L29/739H01L29/417H01L29/861H01L29/08H01L29/872H01L21/20
CPCH01L29/7396H01L29/0847H01L29/7802H01L29/872H01L29/41766H01L29/0634H01L29/7813H01L21/2003H01L29/8611H01L29/1095H01L29/66727H01L29/66734H01L21/324H01L29/7397
Inventor A·瓜尼拉M·G·萨吉奥F·弗里西纳
Owner STMICROELECTRONICS SRL