Heterogeneous processors sharing a common cache

Abstract

The invention discloses a multi-core processor capable of providing a heterogeneous processors core and sharing high-speed cache, which comprises a processor core with the heterogeneous processors core and the high-speed cache connected to the processor core and shared by the processor core; wherein the processor core and the high-speed cache are integrated into a single integrated chip.

Description

[0001] This application is a divisional application of the following application. The filing date of the original application is November 18, 2005. The title of the invention is "Heterogeneous Processor Sharing Common Cache", and the application number is 200510023015.0. technical field [0002] The invention relates to a processor, in particular to a heterogeneous processor sharing a common cache. Background technique [0003] Modern general-purpose processors typically access main memory (typically implemented as dynamic random access memory, or "DRAM") through a hierarchy of one or more caches (eg, L1 and L2 caches). A cache (typically based on static random access memory, or "SRAM") can return data faster than main memory, but uses more area and power. Memories accessed by general-purpose processors typically exhibit high temporal and spatial locality. A cache takes advantage of this by fetching data from main memory in larger chunks than needed (spatial locality) and k...

AI Technical Summary

Problems solved by technology

A cache (typically based on static random-access memory, or "SRAM") can return data faster than main memory, but uses more area and power

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