Method and apparatus for matching velocity
A technology of rate matching and starting position, applied in digital transmission systems, electrical components, error prevention, etc., can solve the problems of large system delay and low processing speed, and achieve the effect of increasing processing speed and reducing system delay
Inactive Publication Date: 2011-09-14
HUAWEI TECH CO LTD
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According to the existing processing flow, the interleaved first check digit and second check digit can only be written into the buffer after all the system bits are written into the buffer. The processing speed of rate matching is low, and the system delay is relatively low. Big
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[0022] In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in further detail below in conjunction with the accompanying drawings.
[0023] See figure 2 The embodiment of the present invention proposes a rate matching method, which can be applied in the baseband processing of the LTE system, for example, in the baseband processing of UE (User Equipment) or base station, so as to accelerate the baseband processing speed and reduce the system The delay.
[0024] The method includes:
[0025] Step 101: The bit stream is subjected to Tubo encoding to obtain three channels of data of systematic bit, first check bit and second check bit, and the three channels of data are respectively subjected to sub-block interleaving;
[0026] See image 3 , Is the typical structure of Turbo encoder: the original information sequence is directly output to obtain systematic bits...
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The embodiment of the invention discloses a rate matching method and a device thereof, which pertain to the field of wireless communication. The method comprises the following steps: bit stream goes through Turbo coding to obtain three paths of data comprising a system bit, a first parity bit and a second parity bit, and subblock interleave is conducted to the three paths of data respectively; the three paths of data after subblock interleave are read and the system bit data in the three paths of data is cached in a first buffer in sequence; the first parity bit data and the second parity bitdata in the three paths of data are cached in a second buffer after data crossing; polling is conducted and data is read from the first buffer and the second buffer until the length of data output meets requirements of rate matching. The device comprises a code interleaving module, a processing module, the first buffer, the second buffer and a reading module. The technical proposal provided by the embodiment of the invention improves the rate matching speed and reduces system delay.
Description
Technical field [0001] The present invention relates to the field of wireless communication, in particular to a rate matching method and device. Background technique [0002] LTE (Long Term Evolution, Long Term Evolution) is the evolution of 3G. It improves and enhances the 3G air access technology, improves the performance of cell edge users, increases cell capacity and reduces system delays, and provides higher levels for future wireless communications. Transmission rate, smaller transmission delay, larger system capacity and coverage. For the baseband processing in the LTE technology, how to speed up the bit-level data processing speed, especially the processing speed of rate matching, is a bottleneck of the entire baseband processing. [0003] The existing turbo coding transmission channel rate matching process is as follows figure 1 As shown, the original bit stream is turbo-encoded to obtain systematic bits, first parity bits, and second parity bits, a total of three output ...
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IPC IPC(8): H04L1/00H04L12/56
Inventor 应君
Owner HUAWEI TECH CO LTD