Low-expense block synchronous method supporting multi-core assisting thread

A block synchronization, low-overhead technology, applied in the field of multi-core computers, can solve the problem that the execution performance of computing threads cannot be improved, and achieve the effect of ensuring sustainable operation ability, reducing synchronization overhead, and improving execution performance.

Inactive Publication Date: 2009-10-21
BEIJING INSTITUTE OF TECHNOLOGYGY
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the current traditional synchronization method, without considering the cost of thread scheduling, for each data access, the prefetch helper thread will synchronize with the computing thread once. This precise synchronization method b...

Method used

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  • Low-expense block synchronous method supporting multi-core assisting thread

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Embodiment Construction

[0068] According to the above technical solutions, the present invention will be described in detail below in conjunction with the examples.

[0069] Take the following simple program as an example, add the ADDSCALE variable in the header file ldsHeader.h, and control the calculation workload of each node in the linked list by changing the value of the variable. The calculation of the linked list nodes is:

[0070] while(iterator){

[0071] temp=iterator->i_data;

[0072] while(i++

[0073] temp+=1;

[0074] }

[0075] res+=temp;

[0076] i=0;

[0077] iterator=iterator->next;

[0078]}

[0079] The calculation workload is adjusted by continuously changing the value of ADDSCALE, starting from ADDSCALE is 0, and the value of ADDSCALE is increased by 5 each time, so that we have ADDSCALE as 0, 5, 10, 15, 20 and so on.

[0080] Combining the above examples, the definitions of relevant terms are given as follows:

[0081] Defi...

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Abstract

The invention relates to a low-expense block synchronous method supporting a multi-core assisting thread, which belongs to the technical field of multi-core computers. The method reduces data missing in the execution of a calculation thread, reduces the pollution to a shared cache, improves the execution performance of the calculation thread and achieves heteronuclear synergic irregular data push by introducing a mechanism of pre-acting and low-expense block synchronization and cycle control for a prefetch assisting thread aiming at the problem of irregular data missing in multi-core application on the basis of a multi-core structure for the sharing cache. The method can be widely applied to optimizing a multi-core compiler and the database performance in the future.

Description

technical field [0001] The invention relates to a low-overhead block synchronization method supporting multi-core helper threads, and belongs to the technical field of multi-core computers. Background technique [0002] On-chip multi-core processor (Chip Multi-Processor) technology is a technology that organically integrates multiple computing cores in a processor chip and uses multi-threading technology to improve the parallel execution performance of applications. According to Amdahl's law, the performance of a program's parallel execution is ultimately determined by the performance of its serial part, and the overhead caused by long-latency memory access in the serial part seriously affects the performance of the application. [0003] Usually, the on-chip multi-core processor architecture has a shared L2 cache (Level 2 Cache) or last level cache (Last level Cache). Traditional hardware prefetch technology can prefetch rule data (such as rule array) in the application pro...

Claims

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Application Information

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IPC IPC(8): G06F9/46G06F12/08G06F12/084G06F12/0862
Inventor 古志民郑宁汉张轶黄艳唐洁刘昌定陈嘉周伟峰张博
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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