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Memory access dispatching device, dispatching method and memory access control system

A memory access and scheduling device technology, applied in the direction of instruments, televisions, electrical digital data processing, etc., can solve problems such as failure to achieve scheduling, achieve the effect of reducing delay, high access efficiency, and reducing the probability of pre-charging

Inactive Publication Date: 2012-03-07
SHANGHAI MAGIMA DIGITAL INFORMATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, even if the bus can well schedule the access sequence to DRAM through it in the most reasonable order, since the DRAM controller contains a cache, those accesses that enter the cache still access the DRAM in the order of FIFO, there is no Achieving Fundamental, Thorough Scheduling

Method used

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  • Memory access dispatching device, dispatching method and memory access control system
  • Memory access dispatching device, dispatching method and memory access control system
  • Memory access dispatching device, dispatching method and memory access control system

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Embodiment Construction

[0042] For ease of description, according to an exemplary embodiment of the present invention, the memory to be accessed includes, for example, four storage banks (Banks), and the regions are divided according to different master devices, and the memory here is, for example, a DRAM. The first storage group B0 and the second storage group B1 are mainly allocated to the CPU, referred to as the CPU storage area; the third storage group B2 and the fourth storage group B3 are mainly allocated to the video processing unit, referred to as the video storage area. To meet certain storage requirements, the CPU also allows access to video storage areas assigned to the video processing unit, namely the third storage group B2 and the fourth storage group B3. It can be understood that in other embodiments, the DRAM can be allocated in other forms. For example, the DRAM can also be divided into more areas and allocated to more master devices, a part of the storage group is allocated to the CP...

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Abstract

The invention relates to a memory access dispatching device and an access dispatching method. The memory access dispatching device comprises an access distribution device, an access dispatching deviceand at least one access array device, wherein the access array device is set according to bus access categories; the access distribution device receives bus access, identifies the bus access categories and distributes the access to a corresponding access array device according to the bus access categories; and the access dispatching device dispatches the access in the access array device and respectively sends out the access according to an order after dispatching. The invention also discloses a memory access control system comprising the memory access dispatching device which is connected tothe system buses and a memory controller which is connected to the memory access dispatching device.

Description

technical field [0001] The invention relates to memory access control, in particular to a DRAM access scheduling device and scheduling method, and a memory access control system. Background technique [0002] Audio and video decoding systems generally use dynamic random access memory (DRAM) as a storage device to store data and control information required by the system. Current designs of dynamic random access memory (DRAM) often employ a shared sense amplifier architecture. DRAMs using this architecture usually have multiple storage banks (banks), and two adjacent access operations to the same row (row) in the same storage bank only need to open the bank in the previous access operation. OK, in the next access operation, there is no need to open the storage group to access directly. However, when the master device accesses a row in a storage group of the DRAM, it is not allowed to access another row in the storage group in the following operation. When another row in th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/18H04N7/26
Inventor 周振亚邓良策
Owner SHANGHAI MAGIMA DIGITAL INFORMATION
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