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Memorizer test device based on scan chain and use method thereof

A technology of memory testing and memory, applied in static memory, instruments, etc., can solve problems such as it is difficult to know memory defects

Inactive Publication Date: 2009-11-25
MAXSCEND TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the memory built-in self-test technology also has some shortcomings. When the chip is tested by the test equipment, it can only detect whether there is a memory defect in the chip, but it is difficult to know which memory is defective.

Method used

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  • Memorizer test device based on scan chain and use method thereof
  • Memorizer test device based on scan chain and use method thereof
  • Memorizer test device based on scan chain and use method thereof

Examples

Experimental program
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Embodiment Construction

[0023] This embodiment includes a memory built-in self-test module, the memory built-in self-test module includes a test vector generation circuit, a built-in self-test control circuit and a memory response analysis circuit; there are at least two memory built-in self-test modules for saving Built-in scannable flip-flops for self-test results, the scannable flip-flops are connected in series to form a scan chain, and the scan chain is controllable and scalable through the port of the memory chip.

[0024] Such as Figure 4 , Figure 5 As shown, the traditional memory built-in self-test module is constructed separately for each RAM and ROM module. The memory built-in self-test module includes three parts: a test vector generation circuit, a BIST control circuit and a response analyzer. The test vector generation circuit can generate a variety of test vectors, and the content of the test vectors generated by circuits implemented by different test algorithms is also different; ...

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PUM

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Abstract

The invention discloses a memorizer test device based on a scan chain and a use method thereof. The invention relates to a test device of a chip and a use method thereof, in particular to a test device of a memorizer and the use method thereof. The invention comprises a memorizer built-in self-test module, and the memorizer built-in self-test module comprises a test vector generating circuit, a built-in self-test control circuit and a memorizer response analysis circuit. A scan-capable trigger used for storing built-in self-test results is arranged in the memorizer built-in self-test module and is connected with a logic circuit scan-capable trigger in series to form the scan chain, and the scan chain is controllable and visible through a port of the chip of the memorizer. The invention can effectively position a defect memorizer without increasing the chip area, and is convenient for defect analysis and design improvement.

Description

technical field [0001] The invention relates to a chip testing device and its usage method, in particular to a memory testing device and its usage method. Background technique [0002] With the continuous shrinking of semiconductor process size, the scale of IC design is getting larger and larger, especially the rapid development of SoC chips, and highly complex SoC chip products are facing high reliability, high quality, low cost and shorter product launch cycle and other increasingly severe challenges. On the one hand, as the size of the semiconductor process shrinks, there are more and more types and quantities of defects that may exist in chips, especially in embedded memories because of the high circuit density, the possibility of defects is greater; on the other hand, as IC products With the increase of the complexity of the chip, the scale of the chip is getting larger and larger, and there are more and more logic circuits in the chip, and the proportion of ROM and R...

Claims

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Application Information

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IPC IPC(8): G11C29/32
Inventor 马伟剑
Owner MAXSCEND TECH