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Adjustable transmitter power for high speed links with constant bit error rate

A transmitter and bit technology, applied in the direction of transmission modification based on link quality, devices dedicated to transmitters, instruments, etc., can solve problems such as consumption

Inactive Publication Date: 2014-03-12
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, additional power may be consumed to ensure accurate data transmission when the same accuracy of data transmission can be achieved with less power

Method used

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  • Adjustable transmitter power for high speed links with constant bit error rate
  • Adjustable transmitter power for high speed links with constant bit error rate
  • Adjustable transmitter power for high speed links with constant bit error rate

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Embodiment Construction

[0020] In the following description, many specific details are stated, such as specific interconnections, specific sigma values, specific signal amplitudes and their scaling factors, specific types, numbers and sizes of test patterns etc. in order to provide a detailed understanding of the present invention. It will be apparent, however, to those skilled in the art that these specific details may be practiced without employing the present invention. In other instances, well-known components or methods, such as specific transmitter and receiver logic, checksum and bit error detection algorithms, interconnection and other operational details of associated logic, have not been described in detail so as not to unnecessarily obscure the present invention .

[0021] The methods and apparatus described herein are for adjusting the amplitude of a transmitter to optimize power consumption. Specifically, adjusting the power of a transmitter is primarily discussed with reference to ill...

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Abstract

A method and apparatus for dynamically adjusting power of a transmitter is herein described. A transmitter transmits a pattern to a receiver at a differential voltage. The length of the pattern, in one embodiment, is selected to be a reasonable length training pattern, as not to incur an extremely long training phase. If errors are detected at the receiver in the pattern, the transmitter steps the differential voltage until errors are not detected in the pattern at the receiver. The differential voltage, where no errors are detected, is scaled by a proportion of a target confidence level to a measured confidence level associated with the reasonable length training pattern. As a result, a training phase is potentially reduced and power is saved while not sacrificing confidence levels in error rates in the data exchange between the transmitter and receiver.

Description

technical field [0001] The present invention relates to high speed links and, in particular, to power savings associated with high speed links. Background technique [0002] As computers have evolved, they have ranged from simple arithmetic calculations to media centers for many media and non-media related applications. Accordingly, computer systems often include many peripheral or input / output devices. In addition, advances in semiconductor technology and computer design have enabled computer systems to include more transistors and processing power on a single physical processor, while also allowing multiple physical processors to reside in a single system. [0003] As a corollary of advances in integrated circuits and their processing capabilities, interconnects between devices have also increased in order to provide adequate bandwidth for high power components. A specific example is that components in an architecture can be coupled using point-to-point links. [0004] ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L25/02G06F13/38
CPCH04L1/20H04L1/0001Y02B60/1235H04L1/0033G06F1/3203G06F1/3253Y02D10/00H04B1/76H04B3/10
Inventor A·马特维克
Owner INTEL CORP