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Method for fast switching parallel pipeline IDCT based on AVS and device thereof

A fast-changing and pipelined technology, applied in the field of digital video coding and decoding, can solve problems such as long running time, low resource utilization, and high ratio of decoder resources.

Inactive Publication Date: 2013-09-25
杭州高特信息技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0031] Each calculation of a pixel requires 16 multiplications and 14 additions, which takes a long time to run, occupies a large proportion of the entire decoder resource, and has low resource utilization.

Method used

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  • Method for fast switching parallel pipeline IDCT based on AVS and device thereof
  • Method for fast switching parallel pipeline IDCT based on AVS and device thereof
  • Method for fast switching parallel pipeline IDCT based on AVS and device thereof

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Embodiment Construction

[0062] The IDCT device of the embodiment of the present invention will be explained in detail below in conjunction with the accompanying drawings.

[0063] The AVS standard uses an 8x8 sub-block as a transformation unit. figure 1 It is a system circuit block diagram of the present invention. In order to understand the specific implementation process of IDCT transformation, the figure 1 The specific functions of various modules are described step by step as follows:

[0064] Step 1, one-dimensional input register module

[0065] Step 1.1, a clock input a residual coefficient, stored in the corresponding register.

[0066]Step 1.2, starting from the first data in an 8x8 block data, output the data in the register in parallel every 8 clocks.

[0067] Step 2, one-dimensional butterfly operation module

[0068] In step 2.1, 8 channels of data are operated in parallel, and the intermediate data is stored in multi-level registers.

[0069] In step 2.2, all operations are shift,...

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Abstract

The invention provides a method for fast switching parallel pipeline IDCT based on AVS and a device thereof. The device comprises a control module, a one-dimensional input register module, a one-dimensional butterfly computing module, a one-dimensional output module, transposition and a ping-pong RAM module, a two dimensional input module, a two dimensional butterfly computing module and a two dimensional output module. By adopting the design idea of parallel pipeline butterfly computing, the invention can constantly fast compute IDCT. Multiplication adopts a method for adding shift, has no multiplying unit, and is applicable to the application of big picture fast AVS video decoding.

Description

Technical field [0001] The invention relates to a device and a method in the technical field of digital video encoding and decoding, in particular to a method and a device for rapid transformation of IDCT (inverse discrete cosine transform) based on parallel pipeline design in the AVS standard. Background technique [0002] With the development of microelectronics technology, the development of electronic information products has become more complex and the time limit for products to market is tight. Therefore, the design of various large-scale circuits for image signal processing is no longer fashionable to adopt full-custom circuit design methods or semi-custom circuit design methods, and the system-level design method using field programmable logic devices has become the development trend of video technology. A new trend. Two-dimensional DCT / IDCT is the core technology in information compression, so it is very necessary to find a fast DCT / IDCT transform suitable for FPGA...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/14H04N7/26H04N19/12H04N19/625
Inventor 陈日仪刘亮
Owner 杭州高特信息技术有限公司