Front-end processed wafer having through-chip connections

Abstract

A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metalization layer. An alternative method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a conductive semiconductor layer.

Description

technical field [0001] The present invention relates to semiconductors, and in particular to electrical connections for such devices. Cross References to Related Applications [0002] This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Application Serial No. 60 / 882,671, filed December 29, 2006, and also as U.S. Patent No. 11 / 422,551, filed June 6, 2006 A continuation of the application, the entire contents of which are hereby incorporated by reference as if fully set forth herein. Background technique [0003] It is often desirable to be able to make electrical connections across a chip in an efficient manner in order to connect it to another component. In most cases, this implies the use of vias and involves connections made near the devices of the chip, as opposed to connections formed on or near the periphery of the chip, as is done conventionally. [0004] One disadvantage of using through-chip vias on fully processed (ie, device-bearing) chip...

AI Technical Summary

Problems solved by technology

[0004] One disadvantage of using through-chip vias on fully processed (i.e., device-bearing) chips is that the fully formed chip is significantly more expensive than the cost of a comparable blank wafer or partially processed chip

If errors are made in the alignment of the vias used for the electrical connection, it may damage the device on the chip or one or more metallization layers, or the desired connection cannot be made

[0005] In both cases, the result may be a useless chip that needs to be scrapped

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