Pulse width modulation control of a matrix converter

[0013] figure 1 It is a schematic view of the power system 10, which receives multi-phase alternating current (AC) power at an input frequency from a power source 12 and provides multi-phase AC power to a load at an output frequency. The power system 10 includes an LC filter 20, a matrix converter 22, and a matrix converter (MxC) controller 24. In the illustrated embodiment, the power supply 12 is a three-phase power supply (including input phases R, S, and T), which provides an input voltage v at the input end of the matrix converter 22 1 , V 2 And v 3 And provide input current i 1 , I 2 And i 3. Also in the illustrated embodiment, the matrix converter 22 provides the induction motor 14 with an output voltage v 1 o , V 2 o And v 3 o And output current i 1 o , I 2 o And i 3 o Three-phase electricity (including U, V and W phases).

[0014] The LC filter 20 includes inductors 26a, 26b, and 26c, and capacitors 28a, 28b, and 28c. The inductor 26a is connected in series with the input phase R, the inductor 26b is connected in series with the input phase S, and the inductor 26c is connected in series with the input phase T. Capacitor 28a is connected across input phases R and S, capacitor 28b is connected across input phases S and T, and capacitor 28c is connected across input phases T and R. The LC filter 20 controls the current level and prevents voltage transients from the power source 12.

[0015] The matrix converter 22 includes switching elements s 11 , S 21 , S 31 , S 12 , S 22 , S 32 , S 13 , S 23 And s 33 (Collectively referred to as s jk ). Switching element s jk For the bidirectional switch connected to the power supply 12 through the LC filter 20, the switching element s 11 , S 12 And s 13 The input voltage v is received on the input node of 1 , In the switching element s 21 , S 22 And s 23 The input voltage v is received on the input node of 2 , And the switching element s 31 , S 32 And s 33 The input voltage v is received on the input node of 3. Connect the switching element s 11 , S 21 And s 31 To provide the output voltage v to the motor 14 1 o , Connect switching element s 12 , S 22 And s 32 To provide the output voltage v to the motor 14 2 o , And connect the switching element s 13 , S 23 And s 33 To provide the output voltage v to the motor 14 3 o. When the matrix converter 22 is shown to receive three-phase power at its input and provide three-phase power at its output, it will be understood that the matrix converter 22 can be adapted to receive power from a power source 12 having any number of phases, and It is suitable for supplying electric power to the electric motor 14 having any number of phases.

[0016] Connect the MxC controller 24 to each switching element s jk To provide the switching function S jk , The switch function S jk Operation switch s jk In order to provide an output signal to the motor 14 at the output frequency. In other words, the MxC controller 24 operates the switching element s jk The frequency of the input signal from the power source 12 is converted into an output frequency that matches the motor 14. MxC controller 24 receives input voltage v 1 , V 2 And v 3 As input and generate switching function S based on these inputs jk. The algorithm used to expand the switch function will be described in more detail below.

[0017] Figure 2A-2C Is suitable for switching element s in matrix converter 22 jk Schematic diagram of the device. Each device receives input voltage v on its input node j And provide output voltage v on its output node k o. Each device is controlled by the switching function S provided by the MxC controller 24 jk And its complementary function S jk. Figure 2A The display device 40 includes a transistor 42 connected in an anti-parallel configuration (emitter to collector) and having a reverse blocking capability. Figure 2B The display device 44 includes a transistor 42 connected in a common collector configuration. Each transistor 42 in device 44 is connected to diode 46 in an anti-parallel configuration to provide opposite conductivity between each transistor 42 and diode 46. Figure 2C The display device 48 includes a transistor 42 connected in a common emitter configuration. Each transistor 42 in device 48 is connected to diode 46 in an anti-parallel configuration to provide opposite conductivity between each transistor 42 and diode 46. In some embodiments, Figure 2A , 2B The transistor 42 in and 2C is an insulated gate bipolar transistor (IGBT). It should be noted that the devices 40, 44, and 48 are only exemplary, and any device that can controllably provide a bidirectional switch between two nodes can be used as the switching element s jk.

[0018] Transistors 42 in devices 40, 44, and 48 may be controlled by pulse width modulation (PWM) signals that provide pulses to the gates of transistors 42 to control the current through them. Can pass the switch function S jk Analog gate pulse, it is assumed that when the switching element s jk The value is "1" when it is off (ie, conductive), and when the switching element s jk The value is "0" when opened. If an inductive load is installed at the output of the matrix converter 22 (for example, the induction motor 14), one of the switching elements s is required jk In a conductive state at any given time. In addition, in order to avoid a short circuit between the input phases R, S and T, the two switching elements s jk Do not conduct electricity at the same time. These constraints can be expressed as:

[0019] X j = 1 n S jk = 1 ; k = 1 , m . - - - ( 1 )

[0020] Following equation 1, for a given k, there are only n-1 independent switching functions S jk. Therefore, the switching function S jk The number is reduced from n×m to (n-1)×m switching functions.

[0021] Such as figure 1 As shown in, by controlling the three switching elements s 1k , S 2k And s 3k To generate output signals for each output phase U, V, and W, the three switching elements s 1k , S 2k And s 3k Corresponds to the three-phase input power from the power supply 12. Therefore, be able to figure 1 The 3×3 matrix converter 22 shown in Figure 2 is regarded as three converters, each containing three input phases and a single output phase, the single output phase having a switching element based on s 1 , S 2 And s 3 Control signal. Output voltage v from three-phase input and single-phase output matrix converter o for:

[0022] v o ( t ) = S 1 ( t ) S 2 ( t ) S 3 ( t ) v 1 ( t ) v 2 ( t ) v 3 ( t ) . - - - ( 2 )

[0023] At short sampling interval T s Using local averaging and assuming the input voltage v 1 , V 2 And v 3 At sampling interval T s Is constant, so Equation 2 can be written as:

[0024] v o =d 1 v 1 +d 2 v 2 +d 3 v 3 , (3)

[0025] Where d 1 , D 2 And d 3 Is defined as d 1，2，3 = T 1，2，3 /T s The duty cycle function. T s Is the time interval T 1 , T 2 And T 3 (Respectively corresponding to the switching element s 1 , S 2 And s 3 Is the sum of the conduction time), and v o Is the locally averaged output voltage. Therefore, according to the duty cycle, Equation 1 can be expressed as:

[0026] d 1 +d 2 +d 3 = 1, (4)

[0027] Where 0≤d 1 , D 2 , D 3 ≤1. Equation 4 shows that since the third duty cycle function can be calculated from two known duty cycle functions, the output voltage v o Is a function of two duty cycle functions.

[0028] Duty cycle function d 1 , D 2 And d 3 Not only can be used to control the output voltage v o , And can be used to provide additional standards that are related to the output current i on a specific input phase in a sampling interval o The distribution is related. Specifically, the input current i 1 , I 2 And i 3 And output current i o The relationship is:

[0029] d 1 i o = I 1;D 2 i o = I 2;D 3 i o = I 3.(5)

[0030] You can choose from the output current i o To input current i 1 , I 2 And i 3 The ratio of the two local average contributions to meet the expected phase shift input voltage v 1 , V 2 And v 3 The ratio is used to control the displacement factor. This can be achieved by introducing the current distribution factor α into the duty cycle function, where the current distribution factor α can be defined as:

[0031] α = i 2 i 3 = d 2 d 3 = v 2 * v 3 * , - - - ( 6 )

[0032] Where the voltage v 2 * And v 3 * Is the phase angle reference voltage. Voltage v 2 * And v 3 * Can be generated by a phase-locked loop (PLL) system, so that they are at the input voltage v 2 And v 3 的相。 The phase.

[0033] To reduce the number of unknown duty cycles from 3 to 2, Equation 4 can be expressed as d 1 = 1-(d 2 +d 3 ), and substitute into Equation 3:

[0034] v o -v 1 =d 2 (v 2 -v 1 )+d 3 (v 3 -v 1 ).(7)

[0035] In addition, Equation 6 can be expressed as d 2 =αd 3 , And substitute into Equation 7 and rewrite it to provide 3 The expression:

[0036] d 3 = v o - v 1 ( v 3 - v 1 ) + α ( v 2 - v 1 ) . - - - ( 8 )

[0037] When the calculated d 3 When the output voltage and input power factor requirements are met, the remaining duty cycle function d can be calculated inversely from equations 4 and 7 1 And d 2.

[0038] image 3 Is used to generate the switching element s 1 , S 2 And s 3 Switch function S 1 , S 2 And S 3 A block diagram of the MxC controller 24 part (referred to as the MxC controller part 24a). The MxC controller part 24a is an embodiment of a system that generates a switching function that meets the constraints outlined above. The MxC controller part 24a includes a phase-locked loop (PLL) module 50, a linear expander module 52, a signal polarity module 54, a level shift module 56, a sorting module 60, a duty cycle module 62, and a pulse width Modulation (PWM) module 64 and demultiplexing module 66. The modules of the MxC controller part 24a can be implemented in the form of hardware, software, firmware, or a combination thereof. In order to provide output signals to all three output phases U, V, and W of the MxC controller 24, three MxC controller sections 24a can be connected in parallel to the input phase from the power supply 12.

[0039] The PLL module 50 receives the input voltage v at its input 1 , V 2 And v 3 And provide the output reference voltage to the linear expander 52 with The linear expander module 52 is based on the output reference voltage v 1 o , V 2 o And v 3 o And zero sequence signal v zs The signal 70 is provided to the signal polarity module 54. The signal polarity module 54 provides a signal 72 to the level shift module 56 based on the signal from the linear expansion module 52 and the polarity signal pol from the duty cycle module 62. The level shift module 56 generates a modified output reference voltage with One of these corrected output reference voltages is provided as an input to the duty cycle module 62.

[0040] The finishing module 60 also receives the input voltage v at its input 1 , V 2 And v 3 And produce a sorted voltage signal v at its output min , V mid And v max , And provide the decoded signal to the demultiplexing module 66. The duty cycle module 62 collects the voltage signal v min , V mid And v max Generate duty cycle signal d min , D mid And d max. The PWM module 64 receives the duty cycle signal d min , D mid And d max Generate switching function S min , S mid And S max , And the demultiplexing module 66 is based on the switching function S min , S mid And S max And the decoded signal from the finishing module 60 provides an output switch function S 1 , S 2 And S 3.

[0041] Sorting module 60 receives input voltage v 1 , V 2 And v 3 , And arrange them as a function of their instantaneous voltage amplitude. Sort input voltage v 1 , V 2 And v 3 , Making v max Is the input phase with the highest amplitude, v min Is the phase with the lowest amplitude, and v mid Is between v max And v min The phase between the amplitudes. The signal v is provided at the output terminal of the sorting module 60 and the input terminal of the duty cycle module 62 max , V mid And v min. The sorting module 60 also provides a decoded signal to the demultiplexing module 66, and the demultiplexing module 66 makes the sorted input voltage v min , V mid And v max The input voltage v of their origin 1 , V 2 And v 3 Associated.

[0042] The PLL module 50 also receives the input voltage v at its input 1 , V 2 And v 3 And generate an output reference voltage at its output with Output reference voltage with Are phase locked and have input voltage v 1 , V 2 And v 3. Output reference voltage to extension with The linearity of the linear expander module 52 provides the output reference voltage with By adding a zero sequence signal v with a specific waveform and amplitude zs Can expand the output reference voltage with Linearity to reduce the output reference voltage with Peak. In some embodiments, the zero sequence signal v zs Is the output reference voltage with The third harmonic of one of them. By appropriately selecting the zero sequence signal v zs , Output reference voltage with The linearity can be Or up to a factor of 15.4% for expansion.

[0043] After the zero sequence signal v zs Increase to output reference voltage with After that, a signal 70 is provided to the polarity module 54. The polarity module 54 receives the polarity signal pol from the duty cycle module 62, the value of which is in the sorted input voltage v mid When it is zero or a positive value, it is "1", and the input voltage v mid When it is a negative value, it is "-1". By ensuring that the criteria listed above are met 0≤d 1 , D 2 , D 3 The polarity signal pol ≤1 amplifies the signal from the linear expander 52.

[0044] Figure 4 Is the input voltage v min , V mid And v max Diagram of the relationship with the polarity signal pol. The input voltage v 1 , V 2 And v 3 Plot the time and enter the voltage v 1 , V 2 And v 3 These are phases that are translated about 120° relative to each other. The line pol shows that the value of the polarity signal pol changes as the polarity of the input voltage with a medium amplitude changes. For example, at instantaneous time T inst , The sorting module 60 sorts the input voltage v 1 , V 2 And v 3 , Making {v 1 , V 2 , V 3 }={v min , V mid , V max }, and because of v mid ≥0, so the polarity signal pol has the value pol=1.

[0045] Back to reference image 3 , The polarity module 54 provides the polarity-adjusted output reference voltage to the level shift module 56 with (Ie, signal 72). The level shift module 56 scales and shifts the signal to provide an input voltage with amplitude up to v 1 , V 2 And v 3 About 86.6% corrected output voltage with The corrected output reference voltage with Is provided to the duty cycle module 62 for calculating the duty cycle function d 1 , D 2 And d 3.

[0046] The duty cycle module 62 receives the sorted input voltage v min , V mid And v max And the corrected output reference voltage with One of the, and generates the duty cycle d min , D mid And d max. Calculate the sampling interval T according to the following table s The duty cycle. Signal v min * , V mid * And v max * Respectively for the phase-locked finishing input reference voltage v min , V mid And v max , Α is the above-mentioned current distribution factor, and ΔV o It is the reference signal provided by the level shift module 56 to the duty cycle module 62.

[0047]

[0048] After calculating the duty cycle function d min , D mid And d max After that, the PWM module 64 generates a modulation function u h m And u l m , They are the duty cycle function d min , D mid And d max The function. In some embodiments, u l m = d mid + d max = ( 1 + α ) d max And u h m = d max . The PWM module 64 modulates the function u h m And u l m Compare with the triangular carrier signal of known frequency to compare the switching element s 1 , S 2 And s 3 Generate a switch function. Figure 5A Is to display the triangular carrier signal v tri Chart with a duty cycle function d plotted on the chart min , D mid And d max And the modulation function u h m And u l m.

[0049] Modulation function u h m And u l m With triangular carrier signal v tri The comparison produces the intermediate switching function S max tc And S mid tc. Figure 5B Is to show the intermediate switch function S max tc And S mid tc Waveform chart. When the triangular carrier signal v tri Less than u h m , The intermediate switch function S max tc It has the logical value "1", and in all other cases the logical value is "0". When the triangular carrier signal v tri Less than u l m , The intermediate switch function S mid tc It has the logical value "1", and in all other cases the logical value is "0".

[0050] Figure 5c is derived from the intermediate switching function S max tc And S mid tc Switch function S min , S mid And S max Chart. Switch function S min , S mid And S max Export as follows:

[0051] S max = S max tc

[0052] S mid = NOT ( S mid tc )

[0053] S min = XOR ( S max tc , S min tc )

[0054] The logic gate can be connected to the traditional triangle comparison hardware to switch the function S from the middle max tc And S mid tc Generate switching function S min , S mid And S max.

[0055] Then, the switch function S is provided to the demultiplexing module 66 min , S mid And S max , The demultiplexing module 66 makes the switch function S based on the decoded signal provided by the classification program block 60 min , S mid And S max And switching element s 1 , S 2 And s 3 Associated. Therefore, to the switching element s 1 Provide switch function S 1 , To the switching element s 2 Provide switch function S 2 , And to the switching element s 3 Provide switch function S 3. Figure 5D Is when v mid When ≥0, the switching element s is controlled separately 1 , S 2 And s 3 Switch function S 1 , S 2 And S 3 The generated waveform chart. Output voltage v to MxC controller part 24a o Is v min , V mid And v max Locally averaged contribution (locally averaged contribution).

[0056] In summary, the present invention relates to the control of a matrix converter including a plurality of switching elements. The matrix converter is adapted to receive a multi-phase alternating current (AC) input signal having an input frequency, and is adapted to generate a multi-phase AC output signal having an output frequency. The phase of these input signals is organized as a function of their instantaneous voltage amplitude. The reference signal is generated from the output reference voltage corresponding to each phase of the output signal. The duty cycle is calculated for each phase of the output signal based on the sorted input signal phase and the reference signal. Then, based on the duty ratio of each phase of the output signal, a switching function that controls one of the switching elements is generated.

[0057] Although the present invention has been described with reference to the preferred embodiments, those skilled in the art will recognize that many changes can be made in form and details without departing from the spirit and scope of the present invention.