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Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM

A convolutional interleaving and deinterleaving technology, applied in the direction of using convolutional code error correction/error detection, data representation error detection/correction, etc., can solve the problems of SDRAM long time, SDRAM performance degradation, etc.

Inactive Publication Date: 2012-11-21
ZHEJIANG UNIV
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AI Technical Summary

Problems solved by technology

When transferring data to non-sequential addresses, because SDRAM takes a long time to gate addresses, the performance of SDRAM will be greatly reduced

Method used

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  • Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM
  • Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM
  • Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM

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Embodiment Construction

[0071] The present invention is applicable to any application scenario requiring convolutional interleaving and deinterleaving techniques.

[0072] like figure 2 As shown, the figure illustrates the system block diagram of convolution (de)interleaving in the present invention. The whole system is composed of convolution (de)interleaving address generator, (de)interleaving and before and after data frame SRAM units (SRAM1 and SRAM2), SDRAM controller and (de)interleaver storage unit SDRAM. The address generator generates the address SDRAM_ADDR in the SDRAM and the address SRAM_ADDR of the (de)interleaved data in the data frame SRAM unit when each branch is (de)interleaved. The relative address of the previous frame interleaved data in each branch is stored in a SRAM unit (SRAM3). In the no-delay branch, the corresponding (de)interleaved data is directly written from the unit of SRAM1 whose address is SRAM_ADDR to the corresponding unit of SRAM2. In the branch with delay, th...

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Abstract

The invention relates to a method for realizing convolution interleaving and de-interleaving of a time domain by using an SDRAM. The prior art has disadvantages. In the method, during interleaving, each interleaved subcircuit is operated according to a sequence of reading before writing, and when the left units, namely the difference between the maximum storage capacity addresses and the relativeaddresses in the current subcircuit, are not enough, the interleaved data is divided into sections to be read and written; and during de-interleaving, each subcircuit is also operated according to the sequence of reading before writing. The method continuously performs address reading and writing on interleaved data of each interleaved subcircuit according to a subcircuit sequence to effectively reduce the time consumed by controlling the SDRAM to frequently searching addresses in the whole interleaving and de-interleaving process and uses the SDRAM to substitute for an FIFO register to further save resources. In addition, the method performs operation of centralized refresh on the SDRAM and cancels the complex stop operation on the SDRAM so as to avoid influence on the continuity of datatransmission.

Description

technical field [0001] The invention belongs to the field of digital communication interleaving, and relates to a method for implementing time-domain convolution interleaving and deinterleaving of transmission data by using SDRAM (synchronous dynamic random access memory) in digital television broadcasting transmission. Background technique [0002] Interleaving is an indispensable part of mobile communication systems. The function of the interleaver is to scramble the sending order of data or data blocks, and the purpose is to reduce burst errors during the transmission of data or data blocks. On the contrary, the function of the deinterleaver is to restore the original data sequence from the scrambled data sequence. [0003] Convolutional interleaving is a type of interleaving technology. A typical convolutional interleaver requires a storage capacity of B×(B-1)×M / 2 symbol units, where the variable B represents the number of interleaving branches, and the variable M repr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/23
Inventor 谢磊陈惠芳李珊王匡
Owner ZHEJIANG UNIV
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