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Dual mosaic method

A technology of dual damascene and dual damascene structure, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of reduced production efficiency and increased waste, and achieve the effect of reducing contact resistance

Inactive Publication Date: 2013-03-27
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the application of this method requires additional steps, which will easily lead to a decrease in production efficiency and an increase in waste products

Method used

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no. 1 example

[0034] As a first embodiment of the present invention, the specific steps of performing a dual damascene operation include:

[0035] First, if image 3 As shown, a dual damascene structure having a via hole 120 and a trench 140 is formed in the dielectric layer 100;

[0036] The dielectric layer 100 can be formed by conventional techniques such as PECVD (Plasma Enhanced Chemical Vapor Deposition), SACVD (Sub-Atmospheric Pressure Chemical Vapor Deposition) or LPCVD (Low Pressure Chemical Vapor Deposition). The dielectric layer 100 can be a low dielectric constant material, and the low dielectric constant material includes but not limited to one of black diamond (Black Diamond, BD) or coral. The dielectric layer material may also include but not limited to undoped silicon dioxide (SiO 2 ), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or one or a combination of materials with a low dielectric constant.

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Abstract

The invention relates to a dual mosaic method, which comprises the following steps of: forming a dual mosaic structure provided with a through hole and a groove in a dielectric layer; determining deposition process parameters containing deposition standard power, wherein the deposition process parameters are used for forming bonding layers with determined thickness on bottom walls and side walls of the through hole and the groove, and the bonding layers formed on the side walls and the bottom wall of the groove are used for preventing metal layers covered on the bonding layers from diffusing into the dielectric layer; adjusting the deposition process parameters, and determining deposition reaction power less than the deposition standard power; forming the bonding layers on the bottom walls and the side walls of the through hole and the groove by using the adjusted deposition process parameters, and ensuring that the thicknesses of the bonding layer formed on the bottom wall of the through hole is less than that of the bonding layer formed on the bottom wall of the groove; removing the bonding layer formed on the bottom wall of the through hole; and forming the metal layer filling the dual mosaic structure. The method can reduce contact resistance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a dual damascene method. Background technique [0002] In the process of integrated circuit design and manufacturing, with copper gaining obvious advantages in chip performance, copper interconnection gradually replaces aluminum metallization and becomes a new trend in the development of integrated circuit interconnection technology. Due to the application of conventional plasma etching process, it is not easy to pattern copper, and when copper is dry etched, no volatile by-products are produced during its chemical reaction, therefore, copper interconnection lines are usually formed by dual damascene process , that is, firstly, forming a dual damascene structure with via holes and trenches in the dielectric layer; then, forming an adhesive layer covering the dual damascene structure; finally, forming an adhesive layer covering the adhesive layer and filling th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
Inventor 聂佳相
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP