Multi-chip packaging structure and manufacturing method thereof
A technology of multi-chip packaging and manufacturing methods, applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve the problems of increasing the overall thickness of the multi-chip packaging structure, increasing the collapse of wire arcs, etc., and avoiding the collapse of welding wires , the overall thickness reduction, the effect of reducing height and length
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[0060] 1A to 1I is a schematic cross-sectional view of a method for manufacturing a chip package structure according to an embodiment of the present invention, and Figure 2A and Figure 2B for Figure 1B top view. First, please refer to Figure 1A , a carrier 110 is provided, and a first chip 120 having a first active surface 122 , a plurality of first pads 124 on the first active surface 122 and a first back surface 126 is arranged on the carrier 110 on. In this embodiment, the carrier 110 is a circuit board, wherein the circuit board can be a FR4, FR5, BT, PI circuit substrate, and the lead frame is made of copper or other suitable conductive materials, for example. from Figure 1A It can be known that when the carrier 110 is a circuit board, it may have a plurality of third solder pads 112 .
[0061] Next, please refer to Figure 1B , place an opening 132 (such as Figure 2A shown) or a notch 132' (such as Figure 2B The relay circuit substrate 130 shown in the d...
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