Sampling hold circuit of clock-controlled floating-gate MOS tube based on threshold cancellation function

Abstract

The invention discloses a sampling hold circuit of a clock-controlled floating-gate MOS tube based on a threshold cancellation function, which comprises a sampling hold circuit based on a clock-controlled floating-gate MOS tube and a threshold cancellation circuit. The drain electrode of a PMOS tube is connected with a second pin of a single-pole double-throw switch, the grid electrode of the PMOS tube is connected with a power supply by a first switch and grounded by a second switch, and the source electrode of the PMOS tube and a substrate are connected with the power supply; and the drain electrode of an NMOS tube is connected with the second pin of the single-pole double-throw switch, the grid electrode of the NMOS tube is connected with the second pin of the single-pole double-throw switch, the source electrode of the NMOS tube and a substrate are grounded, the third pin of the single-pole double-throw switch is grounded, and a first pin of the single-pole double-throw switch is connected with the input grid electrode of the sampling hold circuit based on the clock-controlled floating-gate MOS tube. The threshold voltage of the NMOS tube is extracted by the PMOS tube and the NMOS tube and added to the input grid electrode of a clock-controlled floating-gate NMOS tube, so that the entire circuit achieves the effect of canceling the threshold loss, and the accuracy of the sampling hold circuit is enhanced. The invention has simple structure and very low power consumption.

Description

technical field [0001] The invention relates to an analog signal sampling and holding circuit, in particular to a sampling and holding circuit of a clock-controlled floating-gate MOS transistor based on a threshold cancellation function. technical background [0002] The sample-and-hold operation is the first step in analog signal processing. The analog signal whose amplitude continuously changes is passed through the sample-and-hold circuit to sample the signal value at a certain moment and hold it for a period of time to allow the subsequent circuit to process the signal. The performance of the sample and hold circuit is directly related to the performance of the entire circuit system. Therefore, the sample and hold circuit plays a very important role in the circuit system. In the digital circuit system, as one of the basic circuit units, the analog-to-digital converter ADC, its main performance is determined by the sample and hold circuit. The better the performance of ...

AI Technical Summary

Problems solved by technology

This sample-and-hold circuit has no DC power consumption, and the structure is very simple, so the power consumption is very low, but there is a problem that there is a loss of the threshold voltage of the NMOS tube between the output voltage and the input voltage, because of the existence of this voltage loss, it is greatly The accuracy of the follower circuit is reduced, and when the input voltage is less than the threshold voltage of the NMOS tube, the output voltage of the sample and hold circuit is always 0, and cannot follow the change of the input voltage

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