Parallel computing hardware structure based on separation and combination thought

A parallel computing and thinking technology, applied in the direction of concurrent instruction execution, resource allocation, machine execution device, etc., can solve the problems of high design complexity, reduce design complexity, speed up computing time, and shorten the time of circuit design and implementation Effect

Active Publication Date: 2013-04-10
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, FPGA still needs to use hardware description language for design, and the design complexity is high

Method used

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  • Parallel computing hardware structure based on separation and combination thought
  • Parallel computing hardware structure based on separation and combination thought
  • Parallel computing hardware structure based on separation and combination thought

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Embodiment Construction

[0022] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0023] The present invention proposes a hardware circuit design structure for parallel computing applications. For hardware circuit design problems in practical applications such as parallel computing, the design process is simplified, design efficiency is improved, and parallel computing is fully utilized through the idea of ​​separation and combination. The advantages.

[0024] Such as figure 1 As shown, it is a circuit structure diagram of parallel computing hardware based on the idea of ​​splitting and combining according to the emb...

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Abstract

The invention provides a parallel computing hardware structure based on a separation and combination thought, which comprises a plurality of first parallel computing units, a plurality of second computing units, a task dispatcher used for controlling a plurality of the first parallel computing units and a plurality of the second parallel computing units, a global memory used for storing global data, a local memory for storing intermediate results computed by a plurality of the first parallel computing units and providing the intermediate results to a plurality of the second computing units after starting computation, and a data controller used for providing data for a plurality of the first parallel computing units and the task dispatcher. By adopting the hardware structure applied in parallel computing and provided by the embodiment of the invention, design thoughts such as dispatching, synchronizing and communicating can be effectively covered, so a designer can directly focus on the description of a computation part of an algorithm, thus reducing design complexity of a parallel circuit and shortening circuit design and realization time to a large degree.

Description

technical field [0001] The invention relates to the field of computer and electronic information technology, in particular to a parallel computing hardware structure based on the idea of ​​separation and combination. Background technique [0002] With the rapid increase of computational complexity and data scale, traditional serial processing CPUs are no longer able to handle large-scale complex applications, so how to efficiently solve computational problems has become very important. Utilizing the high degree of parallelism of hardware circuits to accelerate algorithm implementation is an effective way to solve this kind of problems. At the same time, the flexible storage control of hardware circuits makes storage capacity and access speed reliable. However, how to design hardware circuits, make full use of the advantages of hardware circuits such as parallelism, and shield complex issues such as synchronization and scheduling, so as to speed up the time from research and ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F9/50
Inventor 汪玉单羿杨华中
Owner TSINGHUA UNIV
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