MOS structure for inhibiting SOI floating-body effect and manufacturing method thereof

Abstract

The invention discloses an MOS structure for inhibiting SOI floating-body effect. The MOS structure comprises a substrate, a buried insulating layer positioned above the substrate and an active region positioned above the buried insulating layer, wherein the active region comprises a body region, and a first conduction type source region and a first conduction type drain region which are positioned at the two ends of the body region, and a heavily doped second conduction type region positioned between the first conduction type source region and the buried insulating layer; and a gate region is formed above the body region. When the structure is manufactured, the position of the first conduction type source region is subjected to ion implantation by a mask to make a region positioned on the lower part of the first conduction type source region and above the buried insulating layer form the heavily doped second conduction type region. The MOS structure inhibits the floating-body effect effectively, and has the advantages of no increase of chip area, compatibility of a manufacturing process with the conventional CMOS process and the like.

Description

technical field [0001] The invention relates to a MOS (Metal Oxide Semiconductor) structure and a manufacturing method thereof, in particular to a MOS structure capable of effectively suppressing the SOI floating body effect and a manufacturing method thereof, belonging to the technical field of semiconductor manufacturing. Background technique [0002] SOI (Silicon On Insulator) refers to silicon-on-insulator technology. In SOI technology, the device is only manufactured in a very thin silicon film on the surface, and the device and the substrate are separated by a buried oxide layer. It is this structure that makes SOI technology have the incomparable advantages of bulk silicon. The small parasitic capacitance enables SOI devices to have high speed and low power consumption. The full dielectric isolation of SOI CMOS devices completely eliminates the parasitic latch-up effect of bulk silicon CMOS devices, and SOI full dielectric isolation makes SOI technology have high int...

AI Technical Summary

Problems solved by technology

For SOI PMOS, due to the relatively low ionization rate of holes, the electron-hole pairs generated by impact ionization are much lower than that of SOI NMOS, so the Kink effect in SOI PMOS is not obvious

[0005] In order to solve the partially depleted SOI NMOS, the body contact method is usually used to connect the "body" to a fixed potential (source or ground), such as Figure 1a-1b As shown, it is a traditional T-shaped gate structure contact, and the P formed at one end of the T-shaped gate + The injection region is connected to the P-type body region under the gate. When the MOS device is working, the carriers accumulated in the body region pass through the P-type body region. + Channel bleed to achieve the purpose of reducing the potential of the body region. The negative effect is to complicate the process flow, increase the parasitic effect, reduce some electrical properties and increase the device area.

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