FPGA loading method based on ZYNQ chip

Abstract

The invention discloses an FPGA loading method based on a ZYNQ chip. The FPGA loading method comprises the steps of power-on automatic loading during power-on starting and upper computer control loading after a ZYNQ system is started; the power-on automatic loading process is as follows: when the equipment is powered on and started, the loading mode of the FPGA is defaulted to be active loading, and at the moment, the FPGA actively reads a file from Flash2 and rapidly loads the file; the upper computer control loading process comprises the steps that after the ZYNQ system runs, a control daemon process automatically runs, a network port is monitored, and an upper computer command is responded; the upper computer establishes communication with the ZYNQ system by using a network port, a serial port and the like, and issues an FPGA code to be updated; the ZYNQ system receives the data, stores the data in a DDR3 memory, verifies the data and feeds back a verification result to the upper computer; and the ZYNQ system determines an equipment updating mode according to an instruction of the upper computer. The FPGA loading method based on the ZYNQ chip, provided by the invention, has the characteristics that the FPGA is quickly and conveniently updated, and the interruption working time of equipment is short.

Description

technical field [0001] The invention relates to the technical field of FPGA program updating, in particular to a ZYNQ chip-based FPGA loading method. Background technique [0002] At present, most FPGA chips are based on the SRAM structure, and the data in the SRAM unit will be lost after the power is turned off. Therefore, after the system is powered on, the configuration circuit must load the correct configuration data into the SRAM, and the configuration is completed. After power-on, the FPGA enters the working state. After power-off, the FPGA returns to a white chip, and the internal logic relationship disappears. Therefore, the FPGA needs to be reconfigured every time it is powered on. [0003] There are three types of configuration download methods for FPGA devices: active configuration mode, passive configuration mode and JTAG mode; active configuration mode: FPGA acts as a controller every time it is powered on, and the FPGA device guides the configuration operation ...

AI Technical Summary

Problems solved by technology

Among them, the passive configuration mode configures the FPGA through the external CPU. The CPU configures the FPGA to be loaded after the CPU is running. The FPGA cannot be loaded as soon as the power is turned on, so the loading time is longer when the power is turned on.

The loading speed of Flash is fast, but it is troublesome to update the Flash data content. Generally, it is programmed through JTAG before leaving the factory, and it is very troublesome to update the Flash content after leaving the factory.

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