Recess chip packaging structure and laminated packaging structure using same
A chip packaging structure, stacked packaging technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems affecting the signal transmission quality of multi-chip modules, the growth of circuit connection paths, etc.
Inactive Publication Date: 2012-05-23
CHIPMOS TECH INC
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- Abstract
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- Application Information
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Problems solved by technology
However, multiple chips packaged with TSV packaging technology will increase the circuit connection path of the chip stacked on it and packaged with wire bonding packaging technology, which will affect the signal transmission quality of the multi-chip module
Method used
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Embodiment Construction
[0063] Figure 1A A schematic diagram showing a cavity chip packaging structure 10a of the first embodiment of the present invention, and Figure 1B for Figure 1A Partial enlarged view of center I. The cavity chip packaging structure 10 a disclosed in this embodiment includes a plurality of first chips 12 , a substrate 14 a and a plurality of connection points 16 a. Each first chip 12 includes a plurality of vias 18 , a plurality of vias 20 filled in the vias 18 , and a plurality of first pads 22 disposed at two ends of the vias 20 . The configuration of the first pad on the surface of the chip has several forms, one is that the double-sided pad is recessed on the surface of the chip (not shown), and the other is that the pad on one side is recessed on the surface of the chip and opposite One side of the pad is protruded on the chip surface (not shown), and the other is a double-sided pad protruded on the chip surface, such as Figure 1B . The first chips 12 are stacked, a...
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The invention discloses a recess chip packaging structure which comprises a plurality of first chips, a substrate and a plurality of connection points, wherein each first chip comprises a plurality of through holes, a plurality of conduction columns filled in the plurality of through holes and a plurality of first connection pads arranged at two end surfaces of each conduction column, and the plurality of first connection pads of the two adjacent first chips are mutually and electrically conductively connected; the substrate comprises a first surface and a second surface which is opposite to the first surface, wherein the first surface is provided with at least one recess; and the connection points are arranged on at least one of the first surface and the surface at the bottom of the recess, wherein one of the plurality of first chips is electrically connected with the plurality of connection points by means of the plurality of first connection pads. The invention also discloses a laminated packaging structure which uses the recess chip packaging structure.
Description
technical field [0001] The invention relates to a package structure of a semiconductor chip, in particular to a cavity chip package structure and a stacked package structure using the cavity chip package structure. Background technique [0002] Multi-chip modular packaging technology is to combine two or more semiconductor chips in a single package structure. By means of this multi-chip packaging technology into a single package structure, it can not only reduce the footprint of the original integrated circuit package The volume promotes the mobility of high-performance electronic products, and the multi-chip packaging structure can reduce the length of the connecting lines between chips, reduce signal delay and access time, and improve electrical functions. [0003] However, conventional multi-chip module packaging is to package the multi-chip module into a thick package on a planar substrate. Packaging technologies for multi-chip modules include, for example, wire bonding...
Claims
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IPC IPC(8): H01L25/065H01L23/48H01L23/52H01L23/13
CPCH01L2225/06558H01L2224/4824H01L2224/16227H01L2224/16225H01L2924/15321H01L2224/48227H01L2224/13144H01L2224/13147H01L2224/16145H01L2224/32145H01L2224/73253H01L2224/73265H01L2924/15153H01L2924/15156H01L2924/00
Inventor 刘安鸿吴政庭杜武昌侯博凯
Owner CHIPMOS TECH INC