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Silicon wafer with test pads and testing method thereof

A testing method and technology of silicon wafers, which can be used in electronic circuit testing, electrical components, electrical solid-state devices, etc., and can solve problems such as increased manufacturing costs

Active Publication Date: 2012-02-15
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the known technology, slicing must be done after the formation of the trenches 18 to observe its cross-sectional structure, so as to know whether the trenches 18 really penetrate the silicon substrate 11, resulting in increased manufacturing costs.

Method used

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  • Silicon wafer with test pads and testing method thereof
  • Silicon wafer with test pads and testing method thereof
  • Silicon wafer with test pads and testing method thereof

Examples

Experimental program
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Embodiment Construction

[0056] refer to Figure 3 to Figure 6 , is a schematic diagram showing a first embodiment of the method for testing a silicon wafer with test pads according to the present invention. refer to image 3 , providing a silicon wafer 2 . The silicon wafer 2 is the first embodiment of the silicon wafer with test pads of the present invention, which includes a silicon substrate 21 , an insulating layer 22 , at least one test pad 23 and a dielectric layer 24 . The silicon substrate 21 has a first surface 211 and a second surface 212 . The insulating layer 22 is located on the first surface 211 of the silicon substrate 21 . Preferably, the insulation layer 22 is made of silicon oxide, polymer or other materials with insulation properties.

[0057] The test pad 23 is located on the insulating layer 22 and has a surface 231 . The test pad 23 includes a first metal layer 232 , a second metal layer 233 and at least one first inner connection metal 234 . In this embodiment, the test pa...

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PUM

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Abstract

The invention relates to a silicon wafer with a testing weld pad and a testing method thereof. The silicon wafer comprises a silicon base material, an insulating layer, at least one testing weld pad and a dielectric layer, wherein the testing weld pad comprises a first metal layer, a second metal layer and at least one first inner connecting metal, wherein the first metal layer is positioned on the insulating layer and is provided with a first block and a second block; the first block and the second block are mutually electrically independent; the second metal layer is positioned above the first metal layer; and the first inner connecting metal is connected with the second block of the first metal layer and the second metal layer. Thus, when a through hole and a crystal seed layer are formed in a sequential process, whether the crystal seed layer contacts with the second block of the first metal layer of the testing weld pad or not is known trough a test, and then whether the through hole is qualified or not is known, therefore the qualification rate in the sequential process is enhanced.

Description

technical field [0001] The present invention relates to a silicon wafer and a testing method thereof, in particular, to a silicon wafer with testing pads and a testing method thereof. Background technique [0002] Referring to FIG. 1 , a schematic cross-sectional view of a first known silicon wafer is shown. The silicon wafer 1 includes a silicon substrate 11 , an insulating layer 12 , a bonding pad 13 and a dielectric layer 14 . The insulating layer 12 is located on the silicon substrate 11 . The pad 13 is located on the insulating layer 12 . The dielectric layer 14 is located on the insulating layer 12 , covers the pad 13 , and exposes a surface 131 of the pad 13 . [0003] The disadvantages of this known silicon wafer 1 are as follows. When it is desired to form a through hole 19 below the pad 13, the silicon substrate 11 must be etched first to form a through hole 15. However, during the formation of the through hole 15, the etching rate at the center is greater than...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L23/485G01R31/28
CPCH01L24/05H01L2224/05554
Inventor 陈纪翰
Owner ADVANCED SEMICON ENG INC