Method for blocking and awakening transaction threads in hardware transactional memory system

A transaction storage and transaction technology, applied in multi-program devices, concurrent instruction execution, machine execution devices, etc., can solve the problem of difficult migration of transaction buffers, and achieve the effect of optimized and efficient execution

Inactive Publication Date: 2010-12-08
BEIHANG UNIV
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  • Abstract
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  • Claims
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Problems solved by technology

[0005] The purpose of the present invention is to provide a method for blocking and waking up transaction threads in a hardware-type transactional storage system, which removes the restriction that transactions in a hardware-type transactional storage system must be executed within a time slice, and solves the difficulty of migrating transaction buffers The problem of optimizing the efficient execution of transactions in hardware-based transactional storage systems

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  • Method for blocking and awakening transaction threads in hardware transactional memory system
  • Method for blocking and awakening transaction threads in hardware transactional memory system
  • Method for blocking and awakening transaction threads in hardware transactional memory system

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Embodiment Construction

[0030] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0031] see figure 1 As shown, the present invention is a method for blocking and waking up a transaction thread in a hardware type transaction storage system, and the method is implemented as follows:

[0032] Step 1: Wake up the transaction thread

[0033] (A) When the processor starts to execute the transaction, on the one hand, the transaction thread register (TTR) records the identifier activeTID of the currently executed transaction thread;

[0034] (B) on the other hand, record the data of the currently executed transaction in the read / write flag bit of the transaction buffer (TC);

[0035] (C) If the execution time of the transaction thread exceeds a time slice (yes), then block the thread;

[0036] (D) If the execution time of the transaction thread does not exceed a time slice (no), then check whether the transaction is executed, i...

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Abstract

The invention discloses a method for blocking and awakening transaction threads in a hardware transactional memory system, which comprises the following steps of: arranging a transaction thread register in transaction supporting hardware and recording an identifier of a currently-executed transaction thread in the transaction thread register; when a blocked transaction thread is rescheduled and re-executed and if the blocked transaction thread is the same as the thread identifier in the register, continuing to submit the transaction; and if the blocked transaction thread is different from the thread identifier in the register, clearing a current transaction field and re-executing the transaction. The method of the invention has the advantages of eliminating the limitation that the transactions in the hardware transactional memory system are necessarily executed in a time slice, solving the problem that a transaction cache is difficult to migrate and optimizing the high-efficiency execution of the transactions in the hardware transactional memory system.

Description

technical field [0001] The invention relates to a multi-thread parallel programming method belonging to a computer system structure, in particular to a method for blocking and waking up transaction threads in a hardware transaction storage system. Background technique [0002] At present, with the development of technology and application mode, whether it is high-end or low-end, general-purpose or embedded, the traditional instruction-level parallel microprocessor system structure is changing from single-threaded to multi-threaded, single-processor to multi-processing from single-core to multi-core. At the same time, the demand for large-scale data processing in people's applications is also increasing day by day. How to establish an effective programming model so that parallel programs can make full use of these CPUs and cores, give full play to the resource advantages of multi-core processors, fundamentally improve the performance of parallel programs and meet people's co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/46G06F9/38
Inventor 刘轶吴名瑜张昕李鹤张翠
Owner BEIHANG UNIV
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