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Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography

A memory array, memory line technology, applied in the field of memory lines and paths, can solve problems such as expensive

Inactive Publication Date: 2010-12-15
WODEN TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] Formation of deep vias (e.g., vias that span and / or connect multiple levels of memory elements in monolithic 3D memory arrays, also known as Z-vias (Zia) as described below) typically requires the use of relatively expensive advanced etching tools
Additionally, each masking step involved in forming deep vias typically requires the use of relatively expensive advanced immersion lithography tools and techniques
Additionally, deep vias using immersion lithography become more expensive, if not impossible, as feature sizes reach 32nm to 15nm

Method used

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  • Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography
  • Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography
  • Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography

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Embodiment Construction

[0022] The present invention provides a monolithic memory array for forming a three-dimensional memory array (e.g., with multiple levels on a single substrate and / or stacked levels of multiple two-dimensional arrays formed on different substrates and subsequently bonded together) 3D memory array) using a dual depth imprint lithography mask (eg, 3D stencil) to simultaneously form trenches and holes for memory lines and vias, respectively, to adjacent memory levels. More specifically, each line and via is formed using a dual damascene process, wherein the first feature of the dual damascene process can be a word line or a bit line, and the second feature can be a slave word line or a bit line derived path. In some embodiments, a multi-depth imprint lithography mask can be used to simultaneously form trenches for memory lines and access trenches and holes of different depths to, for example, other bit lines and / or Different depth features of word lines, and to adjacent memory le...

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Abstract

The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a damascene process An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a damascene process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to trenches for forming memory lines and at least one depth corresponds to holes for forming vias. Numerous other aspects are disclosed.

Description

[0001] This application claims priority to the following U.S. nonprovisional patent application, the entire contents of which are hereby incorporated by reference: [0002] U.S. Patent Application Serial No. 11 / 967,638, entitled "METHODS AND APPARATUSFORFOMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYSUSING DAMASCENE PROCESS AND IMPRINTLITHOGRAPHY," filed December 31, 2007 (Attorney Docket No. SD-MXD-347); [0003] Cross-Referenced Related Applications [0004] This application is related to the following invention applications, each of which is hereby incorporated by reference in its entirety for all purposes. [0005] U.S. Patent Application Serial No. 10 / 728,451, entitled "High Density Contact to Relaxed Geometry Layers," filed December 5, 2003; [0006] U.S. Patent Application Serial No. 11 / 751,567, entitled "Memory Array Incorporating Memory Cells Arranged in NAND Strings," filed May 21, 2007; [0007] Filed December 31, 2002, entitled "Programmable Memory A...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8239H01L21/027H01L21/28H10B99/00H10B20/00
CPCB82Y10/00H01L2924/0002H01L21/48H01L27/10B82Y40/00G03F7/0002H01L21/76817H01L21/31144H01L27/101H01L23/5384H01L21/76807H01L2221/1021H01L2924/00H10B63/20
Inventor 罗伊·E·肖伊尔莱恩
Owner WODEN TECH INC