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Erasing method and device for non-volatile memory

A technology of non-volatile memory and storage block, which is applied in the field of erasing non-volatile memory devices and devices for erasing non-volatile memory devices, and can solve problems such as low erasing efficiency, time-consuming, and slow speed, and achieve The effect of improving erasing speed and efficiency, saving erasing time, and reducing erasing time

Active Publication Date: 2014-06-11
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Obviously, this serial erasing method is time-consuming
Furthermore, because actually a flash memory includes more memory blocks, the capacity of the flash memory is getting bigger and bigger, and in order to reduce the number of erasing and writing of the Flash, the prior art tends to adopt smaller memory blocks more and more. block as the erasing unit, in this case, there will be more storage blocks in a flash memory, and the method of erasing the entire Flash chip one by one in block units is not only time-consuming, but also faster Slow, the erasing efficiency is relatively low

Method used

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  • Erasing method and device for non-volatile memory
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  • Erasing method and device for non-volatile memory

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Embodiment Construction

[0050] In order to make the above objectives, features and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] In order to enable those skilled in the art to better understand the present invention, the basic principle of the non-volatile memory is briefly introduced below.

[0052] Non-volatile memory is composed of memory cells (cells). The cells include capacitors and transistors. The data in the cell depends on the charge stored in the capacitors. The switching of the transistors controls the access to the data. Generally speaking, a cell can include a source (source, S), a drain (drain, D), a gate (gate, G), and a floating gate (floating gate, FG). FG can be used to connect to the voltage VG. If VG is a positive voltage, a tunneling effect occurs between FG and drain D, causing electrons to be injected into FG, causing ...

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Abstract

The invention discloses an erasing method for a non-volatile memory. The method comprises the following steps of: selecting a target, namely, selecting 2n to-be-erased adjacent memory blocks in the non-volatile memory, wherein n is a natural number; performing pre-programming operation, namely, pre-programming the 2n adjacent memory blocks in groups; erasing, namely, simultaneously erasing the 2n adjacent memory blocks; checking the erasing, namely, checking whether the 2n adjacent memory blocks are successfully erased in groups, if so, performing soft programming operation, and otherwise, returning to the erasing step; and performing the soft programming operation, namely, performing the soft programming operation on the adjacent memory blocks in groups. The method can save erasing time and improve erasing speed and erasing efficiency.

Description

Technical field [0001] The present invention relates to the technical field of semiconductor memory, in particular to a method for erasing a non-volatile memory device and an erasing device of a non-volatile memory device. Background technique [0002] With the rapid development and wide application of various electronic devices and embedded systems, such as computers, personal digital assistants, mobile phones, digital cameras, etc., there is a large need for multiple programming, large capacity, fast reading, writing, and erasing. Convenient, simple, low-cost non-volatile storage device with few peripheral devices (the stored data information can still be maintained in the case of power failure). Non-volatile memory devices have emerged in this context. A non-volatile memory is usually also a MOS transistor, with a source, a drain, a gate, and a floating gate. It can be seen that its structure is slightly different from that of a general MOS tube, with an additional floating ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/10
Inventor 舒清明潘荣华苏志强
Owner GIGADEVICE SEMICON (BEIJING) INC