LED scanning control chip

Abstract

The invention discloses an LED scanning control chip, comprising the following modules of an output amperage adjuster, a constant current source, a counter, a synchronous controller, a sixteen-bit displacement buffer, a state buffer, a comparator, and a buffer memory, and the like. The invention has the advantages that a novel FPGA (Field Programmable Gate Array)-based scanning control chip forms an LED large screen display system together with a peripheral circuit, a display panel and a computer by arranging a synchronous controller, a counter, a displacement buffer, a buffer memory and a comparator: the grey display of 256 levels of the LED display screen is realized; and clear and stable pictures are displayed on the premise of simplifying system hardware structures.

Description

technical field [0001] The invention relates to the field of LED display screens and semiconductor chips, in particular to an LED scanning control chip. Background technique [0002] The LED (light emitting diode) display is composed of an array of light emitting diodes. Light-emitting diode (LED) is a current control device, which has the advantages of high brightness, small size, good monochromaticity, fast response, simple driving, long life, etc. The information publishing task, so it has been widely used. Among them, the LED large screen is composed of LED arrays, through a certain control method to achieve clear playback of text, images, pictures, videos, TV and other signals, its structure adopts the form of standard unit blocks, that is, 8 *16, 16*16, 16*32, 24*24 or 32*32 display pixel lamps constitute a unit module, each module forms an independent electronic scanning function, control function, storage function, and thus constitutes an independent Subsystem, an...

AI Technical Summary

Problems solved by technology

For 256-level grayscale full-screen scanning, high grayscale levels, high scanning frame rate and low memory readout rate are contradictory. To obtain high grayscale levels, the memory readout rate must be increased, or Reduce the frame scanning frequency. When the number of gray levels is high, it is difficult to achieve a balance between the three with the current integrated circuit implementation level. One of the solutions is to use a large number of parallel structures, but the cost will nearly double every time the scanning frequency is reduced. , and the complexity of the circuit will also increase; another method is to properly sacrifice the display efficiency of the screen to obtain a compromise between the frame rate and the rate, using λ=1, t=h / 16, that is, the memory readout rate Equal to the data input rate, the display basic time unit is 1 / 16 of the line period

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